On Thu, Mar 25, 2021 at 06:04:38PM -0600, Robert Hancock wrote:
> This driver was only enabling the first clock on the device, regardless
> of its name. However, this controller logic can have multiple clocks
> which should all be enabled. Add support for enabling additional clocks.
> The clock names used are matching those used in the Xilinx version of this
> driver as well as the Xilinx device tree generator, except for mgt_clk
> which is not present there.
>
> For backward compatibility, if no named clocks are present, the first
> clock present is used for determining the MDIO bus clock divider.
>
> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pan...@xilinx.com>
> Signed-off-by: Robert Hancock <robert.hanc...@calian.com>
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Andrew
