[PATCH net-next v2 01/12] net: phy: marvell10g: rename register

[Marek Behún]

The MV_V2_PORT_MAC_TYPE_* is part of the CTRL register. Rename to
MV_V2_PORT_CTRL_MACTYPE_*.

Signed-off-by: Marek Behún <ka...@kernel.org>
---
 drivers/net/phy/marvell10g.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 74b64e52ffa2..9b514124af0d 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -80,8 +80,8 @@ enum {
        MV_V2_PORT_CTRL         = 0xf001,
        MV_V2_PORT_CTRL_SWRST   = BIT(15),
        MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
-       MV_V2_PORT_MAC_TYPE_MASK = 0x7,
-       MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
+       MV_V2_PORT_CTRL_MACTYPE_MASK = 0x7,
+       MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
        /* Temperature control/read registers (88X3310 only) */
        MV_V2_TEMP_CTRL         = 0xf08a,
        MV_V2_TEMP_CTRL_MASK    = 0xc000,
@@ -477,8 +477,8 @@ static int mv3310_config_init(struct phy_device *phydev)
        val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
        if (val < 0)
                return val;
-       priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
-                       MV_V2_PORT_MAC_TYPE_RATE_MATCH);
+       priv->rate_match = ((val & MV_V2_PORT_CTRL_MACTYPE_MASK) ==
+                       MV_V2_PORT_CTRL_MACTYPE_RATE_MATCH);
 
        /* Enable EDPD mode - saving 600mW */
        return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
-- 
2.26.2