[PATCH v7 net-next 09/15] net: mvpp2: enable global flow control

[stefanc]

From: Stefan Chulski <stef...@marvell.com>

This patch enables global flow control in FW and in the phylink validate mask.

Signed-off-by: Stefan Chulski <stef...@marvell.com>
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h      | 13 ++++++---
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++++++++++++++++++-
 2 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index ca84995..e010410 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
@@ -763,10 +763,12 @@
                ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 
 /* MSS Flow control */
-#define MSS_SRAM_SIZE          0x800
-#define FC_QUANTA              0xFFFF
-#define FC_CLK_DIVIDER         100
-#define MSS_THRESHOLD_STOP     768
+#define MSS_SRAM_SIZE                  0x800
+#define MSS_FC_COM_REG                 0
+#define FLOW_CONTROL_ENABLE_BIT                BIT(0)
+#define FC_QUANTA                      0xFFFF
+#define FC_CLK_DIVIDER                 100
+#define MSS_THRESHOLD_STOP             768
 
 /* RX buffer constants */
 #define MVPP2_SKB_SHINFO_SIZE \
@@ -1021,6 +1023,9 @@ struct mvpp2 {
 
        /* CM3 SRAM pool */
        struct gen_pool *sram_pool;
+
+       /* Global TX Flow Control config */
+       bool global_tx_fc;
 };
 
 struct mvpp2_pcpu_stats {
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 
b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 19a3f38..770f45a 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -92,6 +92,16 @@ static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, 
int cpu)
        return cpu % priv->nthreads;
 }
 
+static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data)
+{
+       writel(data, priv->cm3_base + offset);
+}
+
+static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset)
+{
+       return readl(priv->cm3_base + offset);
+}
+
 static struct page_pool *
 mvpp2_create_page_pool(struct device *dev, int num, int len,
                       enum dma_data_direction dma_dir)
@@ -5951,6 +5961,11 @@ static void mvpp2_phylink_validate(struct phylink_config 
*config,
        phylink_set(mask, Autoneg);
        phylink_set_port_modes(mask);
 
+       if (port->priv->global_tx_fc) {
+               phylink_set(mask, Pause);
+               phylink_set(mask, Asym_Pause);
+       }
+
        switch (state->interface) {
        case PHY_INTERFACE_MODE_10GBASER:
        case PHY_INTERFACE_MODE_XAUI:
@@ -6969,7 +6984,7 @@ static int mvpp2_probe(struct platform_device *pdev)
        struct resource *res;
        void __iomem *base;
        int i, shared;
-       int err;
+       int err, val;
 
        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
        if (!priv)
@@ -7023,6 +7038,10 @@ static int mvpp2_probe(struct platform_device *pdev)
                        return err;
                else if (err)
                        dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
+
+               /* Enable global Flow Control only if handler to SRAM not NULL 
*/
+               if (priv->cm3_base)
+                       priv->global_tx_fc = true;
        }
 
        if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
@@ -7190,6 +7209,15 @@ static int mvpp2_probe(struct platform_device *pdev)
                goto err_port_probe;
        }
 
+       /* Enable global flow control. In this stage global
+        * flow control enabled, but still disabled per port.
+        */
+       if (priv->global_tx_fc && priv->hw_version != MVPP21) {
+               val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
+               val |= FLOW_CONTROL_ENABLE_BIT;
+               mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
+       }
+
        mvpp2_dbgfs_init(priv, pdev->name);
 
        platform_set_drvdata(pdev, priv);
-- 
1.9.1