On Sun, 2020-12-13 at 14:36 +0200, Leon Romanovsky wrote:
> On Sun, Dec 13, 2020 at 02:06:41PM +0200, Leon Romanovsky wrote:
> > From: Parav Pandit <pa...@nvidia.com>
> >
> > MLX5_GENERAL_OBJECT_TYPES types bitfield is 64-bit field.
> >
> > Defining an enum for such bit fields on 32-bit platform results in
> > below
> > warning.
> >
> > ./include/vdso/bits.h:7:26: warning: left shift count >= width of
> > type [-Wshift-count-overflow]
> > ^
> > ./include/linux/mlx5/mlx5_ifc.h:10716:46: note: in expansion of
> > macro ‘BIT’
> > MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
> > ^~~
> >
> > Use 32-bit friendly BIT_ULL macro.
> >
> > Fixes: 2a2970891647 ("net/mlx5: Add sample offload hardware bits
> > and structures")
> > Signed-off-by: Parav Pandit <pa...@nvidia.com>
> > Reported-by: Stephen Rothwell <s...@canb.auug.org.au>
> > Signed-off-by: Leon Romanovsky <leo...@nvidia.com>
> > ---
> > include/linux/mlx5/mlx5_ifc.h | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/include/linux/mlx5/mlx5_ifc.h
> > b/include/linux/mlx5/mlx5_ifc.h
> > index 2006795fd522..8a359b8bee52 100644
> > --- a/include/linux/mlx5/mlx5_ifc.h
> > +++ b/include/linux/mlx5/mlx5_ifc.h
> > @@ -10709,9 +10709,9 @@ struct
> > mlx5_ifc_affiliated_event_header_bits {
> > };
> >
> > enum {
> > - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
> > - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT(0x13),
> > - MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT(0x20),
> > + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
> > BIT_ULL(0xc),
> > + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
> > + MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
>
> Or even better is to use "1ULL << 0x20" directly because we are not
> including bits.h in this mlx5_ifc.h file.
>
> Should I resend?
>
> Thanks
I will change this and attach this patch to my PR of the SF support.
Thanks,
Saeed.
