Hi,
On 12/9/20 1:20 PM, Oleksij Rempel wrote:
> Remove board specific PHY fixup introduced by commit:
>
> | 709bc0657fe6f9f5 ("ARM: imx6ul: add fec MAC refrence clock and phy fixup
> init")
>
> This fixup addresses boards with a specific configuration: a KSZ8081RNA
> PHY with attached clock source to XI (Pin 8) of the PHY equal to 50MHz.
>
> For the KSZ8081RND PHY, the meaning of the reg 0x1F bit 7 is different
> (compared to the KSZ8081RNA). A set bit means:
>
> - KSZ8081RNA: clock input to XI (Pin 8) is 50MHz for RMII
> - KSZ8081RND: clock input to XI (Pin 8) is 25MHz for RMII
OPOS6UL has a KSZ80801RNB. On this PHY variant, bit 7 of reg 0x1F means:
1: RMII 50MHz clock mode; clock input to XI (Pin 9) is 50MHz
0: RMII 25MHz clock mode; clock input to XI (Pin 9) is 25MHz
>
> In other configurations, for example a KSZ8081RND PHY or a KSZ8081RNA
> with 25Mhz clock source, the PHY will glitch and stay in not recoverable
> state.
>
> It is not possible to detect the clock source frequency of the PHY. And
> it is not possible to automatically detect KSZ8081 PHY variant - both
> have same PHY ID. It is not possible to overwrite the fixup
> configuration by providing proper device tree description. The only way
> is to remove this fixup.
>
> If this patch breaks network functionality on your board, fix it by
> adding PHY node with following properties:
>
> ethernet-phy@x {
> ...
> micrel,led-mode = <1>;
> clocks = <&clks IMX6UL_CLK_ENET_REF>;
> clock-names = "rmii-ref";
> ...
> };
On OPOS6UL, this fix do fixes network breakage introduced by this patch.
So, for OPOS6UL,
Tested-by: Sébastien Szymanski <sebastien.szyman...@armadeus.com>
>
> The board which was referred in the initial patch is already fixed.
> See: arch/arm/boot/dts/imx6ul-14x14-evk.dtsi
>
> Signed-off-by: Oleksij Rempel <o.rem...@pengutronix.de>
> ---
> arch/arm/mach-imx/mach-imx6ul.c | 21 ---------------------
> 1 file changed, 21 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
> index e018e716735f..eabcd35c01a5 100644
> --- a/arch/arm/mach-imx/mach-imx6ul.c
> +++ b/arch/arm/mach-imx/mach-imx6ul.c
> @@ -27,30 +27,9 @@ static void __init imx6ul_enet_clk_init(void)
> pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
> }
>
> -static int ksz8081_phy_fixup(struct phy_device *dev)
> -{
> - if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
> - phy_write(dev, 0x1f, 0x8110);
> - phy_write(dev, 0x16, 0x201);
> - } else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
> - phy_write(dev, 0x1f, 0x8190);
> - phy_write(dev, 0x16, 0x202);
> - }
> -
> - return 0;
> -}
> -
> -static void __init imx6ul_enet_phy_init(void)
> -{
> - if (IS_BUILTIN(CONFIG_PHYLIB))
> - phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
> - ksz8081_phy_fixup);
> -}
> -
> static inline void imx6ul_enet_init(void)
> {
> imx6ul_enet_clk_init();
> - imx6ul_enet_phy_init();
> }
>
> static void __init imx6ul_init_machine(void)
>
--
Sébastien Szymanski, Armadeus Systems
Software engineer
