On Fri, May 04, 2007 at 05:54:17PM -0700, Michael Chan wrote:
> + else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
> + ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
> + tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
> + /* Back to back register writes can cause problems on this chip,
> + * the workaround is to read back all reg writes except those to
> + * mailbox regs. See tg3_write_indirect_reg32().
> + *
> + * PCI Express 5750_A0 rev chips need this workaround too.
> + */
> tp->write32 = tg3_write_flush_reg32;
This comment is a little odd now. What about
/*
* Back to back register writes can cause problems on these
* chips, the workaround is to read back all reg writes
* except those to mailbox regs.
*
* See tg3_write_indirect_reg32().
*/
instead?
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