> +#define SPX5_RD_(sparx5, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + readl(spx5_addr((sparx5)->regs, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth))
> +
> +#define SPX5_INST_RD_(iomem, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + readl(spx5_inst_addr(iomem, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth))
> +
> +#define SPX5_WR_(val, sparx5, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + writel(val, spx5_addr((sparx5)->regs, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth))
> +
> +#define SPX5_INST_WR_(val, iomem, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + writel(val, spx5_inst_addr(iomem, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth))
> +
> +#define SPX5_RMW_(val, mask, sparx5, id, tinst, tcnt,
> \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + do { \
> + u32 _v_; \
> + u32 _m_ = mask; \
> + void __iomem *addr = \
> + spx5_addr((sparx5)->regs, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth); \
> + _v_ = readl(addr); \
> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
> + writel(_v_, addr); \
> + } while (0)
> +
> +#define SPX5_INST_RMW_(val, mask, iomem, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + do { \
> + u32 _v_; \
> + u32 _m_ = mask; \
> + void __iomem *addr = \
> + spx5_inst_addr(iomem, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth); \
> + _v_ = readl(addr); \
> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
> + writel(_v_, addr); \
> + } while (0)
> +
> +#define SPX5_REG_RD_(regaddr) \
> + readl(regaddr)
> +
> +#define SPX5_REG_WR_(val, regaddr) \
> + writel(val, regaddr)
> +
> +#define SPX5_REG_RMW_(val, mask, regaddr) \
> + do { \
> + u32 _v_; \
> + u32 _m_ = mask; \
> + void __iomem *_r_ = regaddr; \
> + _v_ = readl(_r_); \
> + _v_ = ((_v_ & ~(_m_)) | ((val) & (_m_))); \
> + writel(_v_, _r_); \
> + } while (0)
> +
> +#define SPX5_REG_GET_(sparx5, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth) \
> + spx5_addr((sparx5)->regs, id, tinst, tcnt, \
> + gbase, ginst, gcnt, gwidth, \
> + raddr, rinst, rcnt, rwidth)
> +
> +#define SPX5_RD(...) SPX5_RD_(__VA_ARGS__)
> +#define SPX5_WR(...) SPX5_WR_(__VA_ARGS__)
> +#define SPX5_RMW(...) SPX5_RMW_(__VA_ARGS__)
> +#define SPX5_INST_RD(...) SPX5_INST_RD_(__VA_ARGS__)
> +#define SPX5_INST_WR(...) SPX5_INST_WR_(__VA_ARGS__)
> +#define SPX5_INST_RMW(...) SPX5_INST_RMW_(__VA_ARGS__)
> +#define SPX5_INST_GET(sparx5, id, tinst) ((sparx5)->regs[(id) + (tinst)])
> +#define SPX5_REG_RMW(...) SPX5_REG_RMW_(__VA_ARGS__)
> +#define SPX5_REG_WR(...) SPX5_REG_WR_(__VA_ARGS__)
> +#define SPX5_REG_RD(...) SPX5_REG_RD_(__VA_ARGS__)
> +#define SPX5_REG_GET(...) SPX5_REG_GET_(__VA_ARGS__)
I don't see any reason for macro magic here. If this just left over
from HAL code? Please turn this all into functions.
Andrew
