> > > On Mon, Nov 23, 2020 at 04:52:40PM +0200, stef...@marvell.com wrote: > > > > From: Stefan Chulski <stef...@marvell.com> > > > > > > > > Tx/Rx FIFO is a HW resource limited by total size, but shared by > > > > all ports of same CP110 and impacting port-performance. > > > > Do not divide the FIFO for ports which are not enabled in DTS, so > > > > active ports could have more FIFO. > > > > > > > > The active port mapping should be done in probe before FIFO-init. > > > > > > It would be nice to know what the effect is from this - is it a > > > small or large boost in performance? > > > > I didn't saw any significant improvement with LINUX bridge or > > forwarding, but this reduced PPv2 overruns drops, reduced CRC sent errors > with DPDK user space application. > > So this improved zero loss throughput. Probably with XDP we would see a > similar effect. > > > > > What is the effect when the ports on a CP110 are configured for 10G, > > > 1G, and 2.5G in that order, as is the case on the Macchiatobin board? > > > > Macchiatobin has two CP's. CP1 has 3 ports, so the distribution of FIFO > > would > be the same as before. > > On CP0 which has a single port, all FIFO would be allocated for 10G port. > > Your code allocates for CP1: > > 32K to port 0 (the 10G port on Macchiatobin) 8K to port 1 (the 1G dedicated > ethernet port on Macchiatobin) 4K to port 2 (the 1G/2.5G SFP port on > Macchiatobin) > > I'm questioning that allocation for port 1 and 2.
Yes, but this allocation exists also in current code. >From HW point of view(MAC and PPv2) maximum supported speed in CP110: port 0 - 10G, port 1 - 2.5G, port 2 - 2.5G. in CP115: port 0 - 10G, port 1 - 5G, port 2 - 2.5G. So this allocation looks correct at least for CP115. Problem that we cannot reallocate FIFO during runtime, after specific speed negotiation. Regards.
