On Thu, 16 Jul 2020 21:10:03 +0300 akiy...@amazon.com wrote: > This patch doesn't require smp_rmb() instruction in the napi routine > because it assumes cache coherency between two cores. I.e. the > 'interrupts_masked' flag set would be seen by the napi routine, even if > the flag is stored in L1 cache. > To the best of my knowledge this assumption holds for ARM64 and x86_64 > architecture which use a MESI like cache coherency model.
If that's the case - for those architectures smb_rmb() should be defined to barrier(). Why can't you adhere to kernel's memory model, rather than guessing the architecture in the driver.
