If present, sources the fec's PTP clock straight from the enet PLL, instead of having to be routed via a SoC pad.
This is only possible on certain SoCs, notably the imx6 (quad) plus. Signed-off-by: Sven Van Asbroeck <thesve...@gmail.com> --- Tree: v5.8-rc3 Patch history: see [PATCH v5 3/3] To: Shawn Guo <shawn...@kernel.org> To: Andy Duan <fugang.d...@nxp.com> To: Rob Herring <robh...@kernel.org> Cc: "David S. Miller" <da...@davemloft.net> Cc: Jakub Kicinski <k...@kernel.org> Cc: netdev@vger.kernel.org Cc: devicet...@vger.kernel.org Cc: Sascha Hauer <s.ha...@pengutronix.de> Cc: Pengutronix Kernel Team <ker...@pengutronix.de> Cc: Fabio Estevam <feste...@gmail.com> Cc: NXP Linux Team <linux-...@nxp.com> Cc: linux-arm-ker...@lists.infradead.org Cc: linux-ker...@vger.kernel.org Documentation/devicetree/bindings/net/fsl-fec.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 9b543789cd52..e34df25a38f6 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -39,6 +39,9 @@ Optional properties: tx/rx queues 1 and 2. "int0" will be used for queue 0 and ENET_MII interrupts. For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse per second interrupt associated with 1588 precision time protocol(PTP). +- fsl,ptpclk-bypass-pad: If present, sources the fec's PTP clock straight from + the enet PLL, instead of having to be routed via a SoC pad. This is only + possible on certain SoCs, notably the imx6 (quad) plus. Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes -- 2.17.1
