> To recap, my setup features a Cadence GEM that is connected to a 88E1510
> PHY which is then connected to port 4 of the switch (which has an
> internal PHY) through a transformer-less link. I know this is not
> optimal as the speed is limited to 100M by that, but that was the only
> way as all other ports where used up.
This is the important bit you failed to mention. Given the number of
patches on netdev, you should assume anything older than three days
has been forgotten.
Back to Back PHYs for the CPU port has never really been supported.
It does however work if the PHYs are 1G and there are a few boards out
there like this, with their owns having crossed fingers this never
breaks. Because it is not really supported.
I guess you need to work out why PPU is not working for you. I would
not be too surprised if it is because it is the CPU port, it is not
supposed to have a PHY, so it is not enabled.
Andrew
