> So I was already led into reworking the entire series to do this > inlining once, after V1. It then turned out it's a horrible mess to get > everything to compile as modules and built-in and then also only the > parallel/SPI as a module and then the other way around.
Maybe consider some trade offs. Have both sets of accessors in the core, and then thin wrappers around it to probe on each bus type. You bloat the core, but avoid the indirection. You can also have the core as a standalone module, which exports symbols for the wrappers to use. It does take some Kconfig work to get built in vs modules correct, but there are people who can help. It is also not considered a regression if you reduce the options in terms of module vs built in. Andrew
