Hello, This series introduces the PTP Hardware Clock (PHC) support to the Mscc Ocelot switch driver. In order to make use of this, a new register bank is added and described in the device tree, as well as a new interrupt. The use this bank and interrupt was made optional in the driver for dt compatibility reasons.
Patches 2 and 4 should probably go through the MIPS tree. Thanks! Antoine Antoine Tenart (8): Documentation/bindings: net: ocelot: document the PTP bank MIPS: dts: mscc: describe the PTP register range Documentation/bindings: net: ocelot: document the PTP ready IRQ MIPS: dts: mscc: describe the PTP ready interrupt net: mscc: describe the PTP register range net: mscc: improve the frame header parsing readability net: mscc: remove the frame_info cpuq member net: mscc: PTP Hardware Clock (PHC) support .../devicetree/bindings/net/mscc-ocelot.txt | 20 +- arch/mips/boot/dts/mscc/ocelot.dtsi | 7 +- drivers/net/ethernet/mscc/ocelot.c | 382 +++++++++++++++++- drivers/net/ethernet/mscc/ocelot.h | 47 ++- drivers/net/ethernet/mscc/ocelot_board.c | 139 ++++++- drivers/net/ethernet/mscc/ocelot_ptp.h | 41 ++ drivers/net/ethernet/mscc/ocelot_regs.c | 11 + 7 files changed, 615 insertions(+), 32 deletions(-) create mode 100644 drivers/net/ethernet/mscc/ocelot_ptp.h -- 2.21.0
