[PATCH V3 6/7] can: flexcan: add ISO CAN FD feature support

[Joakim Zhang]

ISO CAN FD is introduced to increase the failture detection capability
than non-ISO CAN FD. The non-ISO CAN FD is still supported by FlexCAN so
that it can be used mainly during an intermediate phase, for evaluation
and development purposes.

Therefore, it is strongly recommended to configure FlexCAN to the ISO
CAN FD protocol by setting the ISOCANFDEN field in the CTRL2 register.

NOTE: if you only set "fd on", driver will use ISO FD MODE by default.

Signed-off-by: Joakim Zhang <qiangqing.zh...@nxp.com>

ChangeLog:
----------
V1->V2:
        *None
V2->V3:
        *correct a mistake: flexcan_read()/write()->priv->read()/write()
---
 drivers/net/can/flexcan.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index ca7240d69042..ed3463582dc1 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -92,6 +92,7 @@
 #define FLEXCAN_CTRL2_MRP              BIT(18)
 #define FLEXCAN_CTRL2_RRS              BIT(17)
 #define FLEXCAN_CTRL2_EACEN            BIT(16)
+#define FLEXCAN_CTRL2_ISOCANFDEN       BIT(12)
 
 /* FLEXCAN memory error control register (MECR) bits */
 #define FLEXCAN_MECR_ECRWRDIS          BIT(31)
@@ -1276,6 +1277,7 @@ static int flexcan_chip_start(struct net_device *dev)
                reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR3(0x3) | 
FLEXCAN_FDCTRL_MBDSR2(0x3) |
                                FLEXCAN_FDCTRL_MBDSR1(0x3) | 
FLEXCAN_FDCTRL_MBDSR0(0x3));
                reg_mcr = priv->read(&regs->mcr) & ~FLEXCAN_MCR_FDEN;
+               reg_ctrl2 = priv->read(&regs->ctrl2) & 
~FLEXCAN_CTRL2_ISOCANFDEN;
 
                /* support BRS when set CAN FD mode
                 * 64 bytes payload per MB and 7 MBs per RAM block by default
@@ -1286,10 +1288,14 @@ static int flexcan_chip_start(struct net_device *dev)
                        reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR3(0x3) | 
FLEXCAN_FDCTRL_MBDSR2(0x3) |
                                        FLEXCAN_FDCTRL_MBDSR1(0x3) | 
FLEXCAN_FDCTRL_MBDSR0(0x3);
                        reg_mcr |= FLEXCAN_MCR_FDEN;
+
+                       if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
+                               reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
                }
 
                priv->write(reg_fdctrl, &regs->fdctrl);
                priv->write(reg_mcr, &regs->mcr);
+               priv->write(reg_ctrl2, &regs->ctrl2);
        }
 
        if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
@@ -1779,7 +1785,7 @@ static int flexcan_probe(struct platform_device *pdev)
 
        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
                if (priv->devtype_data->quirks & 
FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
-                       priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
+                       priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | 
CAN_CTRLMODE_FD_NON_ISO;
                        priv->can.bittiming_const = &flexcan_fd_bittiming_const;
                        priv->can.data_bittiming_const = 
&flexcan_fd_data_bittiming_const;
                } else {
-- 
2.17.1