When testing I figured out that most operations signal finish even before we trigger the first delay. Seems like PCI(e) access and memory barriers typically add enough latency. Therefore move the first delay after the first check.
Signed-off-by: Heiner Kallweit <hkallwe...@gmail.com> --- drivers/net/ethernet/realtek/r8169.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index 4f1b6e97f..8c41b74ce 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -775,9 +775,9 @@ static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, int i; for (i = 0; i < n; i++) { - delay(d); if (c->check(tp) == high) return true; + delay(d); } netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n", c->msg, !high, n, d); -- 2.21.0