Hello!
On 03/07/2019 01:24 PM, Simon Horman wrote:
> From: Masaru Nagai <masaru.nagai...@renesas.com>
>
> Hardware has the CBS (Credit Based Shaper) which affects only Q3
> and Q2. When updating the CBS settings,
We seem to only write the defaults into TCG, not update them below...
Do we really use TX queues 2/3? I though the driver only uses TX queues
0/1...
> even if the driver does so
> after waiting for Tx DMA finished, there is a possibility that frame
> data still remains in TxFIFO.
>
> To avoid this, decrease TxFIFO depth of Q3 and Q2 to one.
>
> This patch has been exercised this using netperf TCP_MAERTS, TCP_STREAM
> and UDP_STREAM tests run on an Ebisu board. No performance change was
> detected, outside of noise in the tests, both in terms of throughput and
> CPU utilisation.
> Fixes: c156633f1353 ("Renesas Ethernet AVB driver proper")
> Signed-off-by: Masaru Nagai <masaru.nagai...@renesas.com>
> Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi...@renesas.com>
> [simon: updated changelog]
> Signed-off-by: Simon Horman <horms+rene...@verge.net.au>
> ---
> drivers/net/ethernet/renesas/ravb_main.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> b/drivers/net/ethernet/renesas/ravb_main.c
> index d28c8f9ca55b..8154b38c08f7 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -458,7 +458,7 @@ static int ravb_dmac_init(struct net_device *ndev)
> RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
>
> /* Set FIFO size */
> - ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC);
> + ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
Looks harmless... and DaveM has already merged it anyway. :-)
MBR, Sergei
