>On Fri, Feb 22, 2019 at 08:12:42PM +0000, Parshuram Thombare wrote:
>> This patch modify MDIO read/write functions to support communication
>> with C45 PHY in Cadence ethernet controller driver.
>>
>> Signed-off-by: Parshuram Thombare <pthom...@cadence.com>
>> ---
>> drivers/net/ethernet/cadence/macb.h | 15 +++++--
>> drivers/net/ethernet/cadence/macb_main.c | 61
>++++++++++++++++++++++++-----
>> 2 files changed, 61 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/cadence/macb.h
>> b/drivers/net/ethernet/cadence/macb.h
>> index bed4ded..59c23e0 100644
>> --- a/drivers/net/ethernet/cadence/macb.h
>> +++ b/drivers/net/ethernet/cadence/macb.h
>> @@ -636,10 +636,17 @@
>> #define GEM_CLK_DIV96 5
>>
>> /* Constants for MAN register */
>> -#define MACB_MAN_SOF 1
>> -#define MACB_MAN_WRITE 1
>> -#define MACB_MAN_READ 2
>> -#define MACB_MAN_CODE 2
>> +#define MACB_MAN_C22_SOF 1
>> +#define MACB_MAN_C22_WRITE 1
>> +#define MACB_MAN_C22_READ 2
>> +#define MACB_MAN_C22_CODE 2
>> +
>> +#define MACB_MAN_C45_SOF 0
>> +#define MACB_MAN_C45_ADDR 0
>> +#define MACB_MAN_C45_WRITE 1
>> +#define MACB_MAN_C45_POST_READ_INCR 2
>> +#define MACB_MAN_C45_READ 3
>> +#define MACB_MAN_C45_CODE 2
>>
>> /* Capability mask bits */
>> #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
>> diff --git a/drivers/net/ethernet/cadence/macb_main.c
>> b/drivers/net/ethernet/cadence/macb_main.c
>> index 4f4f8e5..2494abf 100644
>> --- a/drivers/net/ethernet/cadence/macb_main.c
>> +++ b/drivers/net/ethernet/cadence/macb_main.c
>> @@ -323,11 +323,30 @@ static int macb_mdio_read(struct mii_bus *bus, int
>mii_id, int regnum)
>> struct macb *bp = bus->priv;
>> int value;
>>
>> - macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
>> - | MACB_BF(RW, MACB_MAN_READ)
>> - | MACB_BF(PHYA, mii_id)
>> - | MACB_BF(REGA, regnum)
>> - | MACB_BF(CODE, MACB_MAN_CODE)));
>> + if (regnum & MII_ADDR_C45) {
>> + macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
>> + | MACB_BF(RW, MACB_MAN_C45_ADDR)
>> + | MACB_BF(PHYA, mii_id)
>> + | MACB_BF(REGA, (regnum >> 16) & 0x1F)
>> + | MACB_BF(DATA, regnum & 0xFFFF)
>> + | MACB_BF(CODE, MACB_MAN_C45_CODE)));
>> +
>> + /* wait for end of transfer */
>> + while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
>> + cpu_relax();
>
>You need a timeout here, and anywhere you wait for the hardware to complete.
>Try to make use of readx_poll_timeout() variants.
>
> Andrew
Yes, I will add timeout here.
Regards,
Parshuram Thombare
