On Mon, Feb 18, 2019 at 06:33:51PM +0530, Vinod Koul wrote:
> +     case PHY_INTERFACE_MODE_RGMII_ID:
> +             /* RGMII_ID needs internal delay. This is enabled through
> +              * PORT5_PAD_CTRL for all ports, rather than individual port
> +              * registers
> +              */
> +             qca8k_write(priv, reg,
> +                         QCA8K_PORT_PAD_RGMII_EN |
> +                         QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
> +                         QCA8K_PORT_PAD_RGMII_RX_DELAY(3));

Hi Vinod

Could you add some #defines for the delay values?

    Thanks
        Andrew

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