From: Maxime Chevallier <maxime.chevall...@bootlin.com> Date: Fri, 15 Feb 2019 09:33:47 +0100
> The PHY core expects PHY drivers not to set Pause and Asym_Pause bits, > unless the driver only wants to specify one of them due to HW > limitation. In the case of the Marvell10g driver, we don't need to set > them. > > Signed-off-by: Maxime Chevallier <maxime.chevall...@bootlin.com> > Suggested-by: Andrew Lunn <and...@lunn.ch> Applied, thanks.
