On 04.02.2019 22:28, Andrew Lunn wrote: > On Mon, Feb 04, 2019 at 10:03:21PM +0100, Heiner Kallweit wrote: >> Add support for speeds 10Mbps, 5Gbps, and 10Gbps. In addition don't >> hardcode duplex but read it from the chip. > > Hi Heiner > > The marvell10g does this differently. It gets the local and link > partner advertised link modes and from that works out what the PHY is > doing. If auto-neg is not being used, it then reads the link speed > from the PMA. > Right, it's the same mechanism we use in genphy_read_status() for clause 22.
> The question is, should the Aquantia PHY do the same, or should it > look an vendor registers? Apart from getting the 1G advertisement, all > the Marvell code uses generic registers. So we should be able to move > most of it into phy-c45 and reuse it. That is what i would prefer. > I'd like to use standard registers wherever possible. This patch is meant as a quick win to improve what we do already in aqr_read_status. Once we have a generic c45 read_status function we should switch to it. However I assume that information like interface mode we still have to read from vendor registers. > Andrew > Heiner
