Den tis 15 jan. 2019 kl 16:39 skrev Christoph Hellwig <h...@infradead.org>: > > Hmm, while the RISC-V spec requires misaligned load/store support, > who says they are efficient? Maybe add a little comment that says > on which cpus they are efficient.
Good point! :-) I need to check how other architectures does this. Enabling it for *all* RV64 is probably not correct.
