Hi Bhadram, On 15-05-2018 07:44, Bhadram Varka wrote: > Hi Jose, > > On 5/10/2018 9:15 PM, Jose Abreu wrote: >> >> >> On 10-05-2018 16:08, Bhadram Varka wrote: >>> Hi Jose, >>> >>> On 5/10/2018 7:59 PM, Jose Abreu wrote: >>>> Hi Bhadram, >>>> >>>> On 10-05-2018 09:55, Jose Abreu wrote: >>>>> ++net-dev >>>>> >>>>> Hi Bhadram, >>>>> >>>>> On 09-05-2018 12:03, Bhadram Varka wrote: >>>>>> Hi, >>>>>> >>>>>> Thanks for responding. >>>>>> >>>>>> Tried below suggested way. Still observing the issue - >>>>> It seems stmmac has a bug in the RX side when using TSO >>>>> which is >>>>> causing all the RX descriptors to be consumed. The stmmac_rx() >>>>> function will need to be refactored. I will send a fix ASAP. >>>> >>>> Are you using this patch [1] ? Because there is a problem with >>>> the patch. By adding the previously removed call to >>>> stmmac_init_rx_desc() TSO works okay in my setup. >>>> >>> >>> No. I don't have this change in my code base. I am using >>> net-next tree. >>> >>> Can you please post the change for which TSO works ? I can help >>> you with the testing. >> >> It should work with net-next because patch was not merged yet ... >> Please send me the output of "dmesg | grep -i stmmac", since boot >> and your full register values (from 0x0 to 0x12E4). >> > > [root@alarm ~]# dmesg | grep -i dwc > [ 6.925005] dwc-eth-dwmac 2490000.ethernet: Cannot get CSR > clock > [ 6.933657] dwc-eth-dwmac 2490000.ethernet: no reset control > found > [ 6.955325] dwc-eth-dwmac 2490000.ethernet: User ID: 0x10, > Synopsys ID: 0x41 > [ 6.962379] dwc-eth-dwmac 2490000.ethernet: DWMAC4/5 > [ 6.967434] dwc-eth-dwmac 2490000.ethernet: DMA HW > capability register supported > [ 6.974827] dwc-eth-dwmac 2490000.ethernet: RX Checksum > Offload Engine supported > [ 6.982915] dwc-eth-dwmac 2490000.ethernet: TX Checksum > insertion supported > [ 6.991235] dwc-eth-dwmac 2490000.ethernet: Wake-Up On Lan > supported > [ 6.998974] dwc-eth-dwmac 2490000.ethernet: TSO supported > [ 7.006422] dwc-eth-dwmac 2490000.ethernet: TSO feature enabled > [ 7.012581] dwc-eth-dwmac 2490000.ethernet: Enable RX > Mitigation via HW Watchdog Timer > [ 7.236391] dwc-eth-dwmac 2490000.ethernet eth0: device MAC > address 4a:d1:e3:58:cb:7a > [ 7.333414] dwc-eth-dwmac 2490000.ethernet eth0: IEEE > 1588-2008 Advanced Timestamp supported > [ 7.342441] dwc-eth-dwmac 2490000.ethernet eth0: registered > PTP clock > [ 10.157066] dwc-eth-dwmac 2490000.ethernet eth0: Link is Up > - 1Gbps/Full - flow control off > [root@alarm ~]# dmesg | grep -i stmma > [ 7.020567] libphy: stmmac: probed > [ 7.316295] Broadcom BCM89610 stmmac-0:00: attached PHY > driver [Broadcom BCM89610] (mii_bus:phy_addr=stmmac-0:00, irq=64) > > I will get the register details - > > FYI - TSO works fine with single channel. I see the issue only > if multi channel enabled (supports 4 Tx/Rx channels). >
And normal data transfer works okay with multi channel, right? I will need the register details to proceed ... You could also try git bisect ... Thanks and Best Regards, Jose Miguel Abreu
