On Wed, 2018-03-28 at 12:13 +0200, Lino Sanfilippo wrote: > Hi, > > > > > > Yeah so that other trick I'm talking about is also used for timing > > accuracy. > > > > For example, let's say I have a device with a reset bit and the spec > > says the reset bit needs to be set for at least 10us. > > > > This is wrong: > > > > writel(1, RESET_REG); > > usleep(10); > > writel(0, RESET_REG); > > > > Because of write posting, the first write might arrive to the device > > right before the second one. > > > > Does not write posting only concern PCI? This seems to be a different topic. > Furthermore > write posting should not include write reordering...
Nobody's talking about re-ordering and no, write posting is rather common practice on a whole lot of different busses, not just PCI(e). Cheers, Ben.
