Hi, I am alarmed and embarassed that sloppy comments on my part has turned onto a long conversation.
On Wed, Sep 20, 2006 at 02:58:39AM +0200, Segher Boessenkool wrote: > >> Sure, PCI busses are little-endian. But is readX()/writeX() for PCI > >> only? I sure hope not. > > > > It's defined for PCI and possibly ISA memory. You can use it for other > > things if you whish to, but "other things" are arch specific in any > > case. > > Huh? You're saying that only PCI and ISA are standardised busses? Well, I'm having trouble thinking of other busses that have as strong a sense of the "address-data" style I/O as PCI. Busses like scsi and ide are primarily "command-data" or "data-data" in style. Only the address-data style busses need readl/writel-style routines. I can't prove, but suspect that the "adress-data" style of access is why PCI is wired up "close to" the CPU. What other bsses are there that are direct-attached to the CPU? I can't think of much ... The sbus on sparc ... hypertransport from AMD ... but hypertransport is more or less invisible to the kernel. ... some recent attempts to supplant the system bus with infiniband, but I get the impression that this will be strangely engineered, and semi-invisible to the kernel as well. The actual infiniband protocols are ipv6-like+rdma and so fall into a "data-data" programming style. > > Different bus -> different accessor. > > Then please rename readX()/writeX() to pci_readX()/pci_writeX(). Well, I don't get the impression that there will be othre busses for which this is an issue the way it is on pci. --linas - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
