FIFOCTL_RXERR and FIFOCTL_TXERR are undocumented bits, according to the
Sigmatel datasheet. We should thus not take any assumption on their values
and semantics.

Problem spotted by andrzej zaborowski <[EMAIL PROTECTED]>
Signed-off-by: Samuel Ortiz <[EMAIL PROTECTED]>

---
 drivers/net/irda/stir4200.c |   15 ---------------
 1 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/drivers/net/irda/stir4200.c b/drivers/net/irda/stir4200.c
index d61b208..12103c9 100644
--- a/drivers/net/irda/stir4200.c
+++ b/drivers/net/irda/stir4200.c
@@ -149,8 +149,6 @@ enum StirFifoCtlMask {
        FIFOCTL_DIR = 0x10,
        FIFOCTL_CLR = 0x08,
        FIFOCTL_EMPTY = 0x04,
-       FIFOCTL_RXERR = 0x02,
-       FIFOCTL_TXERR = 0x01,
 };
 
 enum StirDiagMask {
@@ -615,19 +613,6 @@ static int fifo_txwait(struct stir_cb *s
 
                pr_debug("fifo status 0x%lx count %lu\n", status, count);
 
-               /* error when receive/transmit fifo gets confused */
-               if (status & FIFOCTL_RXERR) {
-                       stir->stats.rx_fifo_errors++;
-                       stir->stats.rx_errors++;
-                       break;
-               }
-
-               if (status & FIFOCTL_TXERR) {
-                       stir->stats.tx_fifo_errors++;
-                       stir->stats.tx_errors++;
-                       break;
-               }
-
                /* is fifo receiving already, or empty */
                if (!(status & FIFOCTL_DIR)
                    || (status & FIFOCTL_EMPTY))
-- 
1.4.1.1

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