From: Niklas Cassel <niklas.cas...@axis.com> Date: Sat, 3 Mar 2018 00:28:53 +0100
> However, the last write we do is "DMA start transmission", > this is a register in the IP, i.e. it is a write to the cache > incoherent MMIO region (rather than a write to cache coherent memory). > To ensure that all writes to cache coherent memory have > completed before we start the DMA, we have to use the barrier > wmb() (which performs a more extensive flush compared to > dma_wmb()). The is an implicit memory barrier between physical memory writes and those to MMIO register space. So as long as you place the dma_wmb() to ensure the correct ordering within the descriptor words, you need nothing else after the last descriptor word write.
