Hi Daniel, > -----Original Message----- > From: Daniel Walker [mailto:danie...@cisco.com] > Sent: Tuesday, April 18, 2017 7:48 PM > To: Andrew Lunn <and...@lunn.ch> > Cc: Florian Fainelli <f.faine...@gmail.com>; Andy Fleming > <aflem...@freescale.com>; Harini Katakam <hari...@xilinx.com>; > netdev@vger.kernel.org; HEMANT RAMDASI <hramd...@cisco.com>; Julius > Hemanth Pitti -X (jpitti - MONTA VISTA SOFTWARE INC at Cisco) > <jpi...@cisco.com> > Subject: Re: Marvell phy errata origins? > > On 04/18/2017 07:04 AM, Andrew Lunn wrote: > > On Tue, Apr 18, 2017 at 06:16:33AM -0700, Daniel Walker wrote:
<snip> > >> In Harini's commit > >> message for , > >> > >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/co > >> mmit/drivers/net/phy/marvell.c?id=3ec0a0f10ceb > >> > >> "This function has a sequence accessing Page 5 and Register 31, both > >> of which are not defined or reserved for this PHY" > >> > >> For the 88E1112 we see that these are "Factory Test Modes" which the > >> contents of are not documented. They aren't really "not defied", and > >> aren't really "reserved" .. Marvell support claims they don't support > >> these drivers, and Freescale seems to be adding these drivers, and > >> the line we are looking at. > >> > >> We had some issues with our PHY which were corrected with the same > >> patch Harini used but modified for the M88E1112. We're trying to get > >> to the bottom of where this code came from and what it was suppose to > >> be doing. > > I tried to find this errata fix in the Marvell reference code. And > > failed to find it. But it is "Vendor Crap" code, hard to find anything > > in it. > > > > My guess is, this errata just applies to one model of PHY, maybe even > > one revision of one model of a PHY. The hard bit is figuring out what > > actually needs it. Do you have access to Marvell datasheets? > I have access to the datasheets for 88E1111, 88E1112 and 88E1116 (and another family 151x) - None of them have these register details or the errata documented. Regards, Harini
