> > +/* Read Phy Hardware Clock */ > > +static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles) > > +{ > > + struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); > > + struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt; > > + u32 temp = 0; > > + > > + temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB); > > + *phc_cycles = qed_rd(p_hwfn, p_ptt, > NIG_REG_TSGEN_SYNC_TIME_MSB); > > + *phc_cycles <<= 32; > > + *phc_cycles |= temp; > > + > > + return 0; > > +} > > LSB and MSB being read non atomically, it looks like you could have an error > of (1<<32) cycles here. > > (You read LSB value close to 0xFFFFFFFF right before it changes to 0, while > MSB got incremented.)
Once we read the LSB, HW latches the MSB until it's read. So it's not an issue [although probably worth a comment].