Hi Raghu, [auto build test WARNING on net-next/master]
url: https://github.com/0day-ci/linux/commits/Raghu-Vatsavayi/liquidio-support-for-new-device-cn23xx/20160804-063711 config: arm64-allmodconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 5.4.0-6) 5.4.0 20160609 reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree make.cross ARCH=arm64 All warnings (new ones prefixed by >>): In file included from include/linux/printk.h:292:0, from include/linux/kernel.h:13, from include/linux/list.h:8, from include/linux/pci.h:25, from drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c:23: drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c: In function 'cn23xx_dump_pf_initialized_regs': >> drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c:102:30: warning: >> format '%lx' expects argument of type 'long unsigned int', but argument 6 >> has type 'u64 {aka long long unsigned int}' [-Wformat=] dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016lx\n", ^ include/linux/dynamic_debug.h:86:39: note: in definition of macro 'dynamic_dev_dbg' __dynamic_dev_dbg(&descriptor, dev, fmt, \ ^ >> drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c:102:2: note: in >> expansion of macro 'dev_dbg' dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016lx\n", ^ vim +102 drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 > 23 #include <linux/pci.h> 24 #include <linux/netdevice.h> 25 #include <linux/vmalloc.h> 26 #include "liquidio_common.h" 27 #include "octeon_droq.h" 28 #include "octeon_iq.h" 29 #include "response_manager.h" 30 #include "octeon_device.h" 31 #include "cn23xx_pf_device.h" 32 #include "octeon_main.h" 33 34 #define RESET_NOTDONE 0 35 #define RESET_DONE 1 36 37 /* Change the value of SLI Packet Input Jabber Register to allow 38 * VXLAN TSO packets which can be 64424 bytes, exceeding the 39 * MAX_GSO_SIZE we supplied to the kernel 40 */ 41 #define CN23XX_INPUT_JABBER 64600 42 43 #define LIOLUT_RING_DISTRIBUTION 9 44 const int liolut_num_vfs_to_rings_per_vf[LIOLUT_RING_DISTRIBUTION] = { 45 0, 8, 4, 2, 2, 2, 1, 1, 1 46 }; 47 48 void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct) 49 { 50 int i = 0; 51 u32 regval = 0; 52 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip; 53 54 /*In cn23xx_soft_reset*/ 55 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n", 56 "CN23XX_WIN_WR_MASK_REG", CVM_CAST64(CN23XX_WIN_WR_MASK_REG), 57 CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG))); 58 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 59 "CN23XX_SLI_SCRATCH1", CVM_CAST64(CN23XX_SLI_SCRATCH1), 60 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1))); 61 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 62 "CN23XX_RST_SOFT_RST", CN23XX_RST_SOFT_RST, 63 lio_pci_readq(oct, CN23XX_RST_SOFT_RST)); 64 65 /*In cn23xx_set_dpi_regs*/ 66 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 67 "CN23XX_DPI_DMA_CONTROL", CN23XX_DPI_DMA_CONTROL, 68 lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL)); 69 70 for (i = 0; i < 6; i++) { 71 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 72 "CN23XX_DPI_DMA_ENG_ENB", i, 73 CN23XX_DPI_DMA_ENG_ENB(i), 74 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i))); 75 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 76 "CN23XX_DPI_DMA_ENG_BUF", i, 77 CN23XX_DPI_DMA_ENG_BUF(i), 78 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i))); 79 } 80 81 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL", 82 CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL)); 83 84 /*In cn23xx_setup_pcie_mps and cn23xx_setup_pcie_mrrs */ 85 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); 86 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", 87 "CN23XX_CONFIG_PCIE_DEVCTL", 88 CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval)); 89 90 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 91 "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port, 92 CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port), 93 lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))); 94 95 /*In cn23xx_specific_regs_setup */ 96 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n", 97 "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port, 98 CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)), 99 CVM_CAST64(octeon_read_csr64( 100 oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)))); 101 > 102 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016lx\n", 103 "CN23XX_SLI_RING_RST", CVM_CAST64(CN23XX_SLI_PKT_IOQ_RING_RST), 104 octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST)); 105 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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