Hi Andrew,
On Jul 7, 2016, at 9:52 AM, Andrew Lunn and...@lunn.ch wrote:
>> Also, note that this indirect access is a single-register which doesn't
>> require to wait for the operation to complete (like Switch MAC, Trunk
>> Mapping, etc.), in contrary to multi-registers indirect accesses with
>> several busy operations (like ATU, VTU, etc.).
>
> Are you sure about this? The DSDT polls bit 15 of the register.
Every single-register operation (with an "Update" bit, "pointer" and "data"
bits) execute in a single write operation and doesn't need to wait for
completion.
But multiple-register operations like ATU, VTU, etc. with a "Busy" bit,
Operation bits and data registers, do require and explicitly mention to wait
for the operation to complete (by polling the busy bit or via interrupt).
We could add checks but it doesn't sound necessary, we are not doing it for
others Update operations and a badly set switch MAC address would be easily
identifiable.
Thanks,
Vivien
