On Friday, June 24, 2016 6:46:48 PM CEST Timur Tabi wrote:
> + /* The EMAC itself is capable of 64-bit DMA. If the SOC limits that
> + * range, then we expect platform code to adjust the mask accordingly.
> + */
> + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
> + if (ret) {
> + dev_err(&pdev->dev, "could not set DMA mask\n");
> + return ret;
> + }
>
The comment does not match the code: if the platform has no IOMMU
and the bus limit is smaller than the memory, dma_set_mask_and_coherent()
will fail, and the driver should instead ensure that the buffers are
allocated from the 32-bit area.
Alternatively, adjust the comment to explain that this is a limitation
in the driver that can be lifted if necessary.
Arnd
