On Thu, Apr 21, 2016 at 10:21 AM, Babu Moger <babu.mo...@oracle.com> wrote: > Current code writes the tx/rx relaxed order without reading it first. > This can lead to unintended consequences as we are forcibly writing > other bits.
The consequences were very much intended as there are situations where enabling relaxed ordering can lead to data corruption. > We noticed this problem while testing VF driver on sparc. Relaxed > order settings for rx queue were all messed up which was causing > performance drop with VF interface. What additional relaxed ordering bits are you enabling on Sparc? I'm assuming it is just the Rx data write back but I want to verify. > Fixed it by reading the registers first and setting the specific > bit of interest. With this change we are able to match the bandwidth > equivalent to PF interface. > > Signed-off-by: Babu Moger <babu.mo...@oracle.com> Fixed is a relative term here since you are only chasing performance from what I can tell. We need to make certain that this doesn't break the driver on any other architectures by leading to things like data corruption. - Alex
