On Tue, Apr 12, 2016 at 12:24 AM, Saeed Mahameed <sae...@dev.mellanox.co.il> wrote: > On Tue, Apr 12, 2016 at 12:17 AM, Or Gerlitz <gerlitz...@gmail.com> wrote:
>> feature --> features > Correct, will fix. >>> * Add vport to steering commands for SRIOV ACL support >>> * Add mlcr, pcmr and mcia registers for dump module EEPROM >>> * Add support for FCS, baeacon led and disable_link bits to hca caps >>> * Add CQE period mode bit in CQ context for CQE based CQ >>> moderation support >>> * Add umr SQ bit for fragmented memory registration >>> * Add needed bits and caps for Striding RQ support >> AFAIK, all the above are features will go through net-next, what made >> you anticipate conflicts with linux-rdma? > FCS bit is needed also for rdma, so we took the liberty of updating > all the needed HW structs, bits, caps, etc .. > at once for all mlx5 features planned for 4.7 regardless of rdma/net > conflicts. The cover letter states that this series deals with shared code. I guess you might also could extend it a bit to deal also with code that you suspect could lead to conflicts, but I don't see why it evolved to that extent. Or.
