From: Jisheng Zhang <jszh...@marvell.com> Date: Wed, 30 Mar 2016 19:53:41 +0800
> The mvpp2 ip maybe used in SoCs which may have have 64bytes cacheline > size. Replace the MVPP2_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES. > > And since dma_alloc_coherent() is always cacheline size aligned, so > remove the align checks. > > Signed-off-by: Jisheng Zhang <jszh...@marvell.com> Applied.
