Ayaz Abdulla wrote:
+
+ NvRegPowerState2 = 0x600,
+#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
+#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
};
If the nic has a register 0x600, then we should
- ioremap enough memory. Right now, the code only remaps 0x270
- report all registers for ethtool, right now only 0x400 bytes are dumped.
+static void nv_mac_reset(struct net_device *dev)
+{
+ struct fe_priv *np = netdev_priv(dev);
+ u8 __iomem *base = get_hwbase(dev);
+
+ dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
+ writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits,
base + NvRegTxRxControl);
+ pci_push(base);
+ writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
+ udelay(NV_MAC_RESET_DELAY);
Do not add udelay's after writel without a pci_push:
Nothing guarantees that the writel won't wait in the pci bridge - writes
can be posted. And that would break the timing.
Just add a pci_push() before the udelay. It reads from the nic, that
forces the pci bridge to send the write command to the device.
--
Manfred
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