Could everyone who has problems with hangs try the following patch (against
current 2.6.16-rc3 version)
If it gets mangled (it's also at
http://developer.osdl.org/shemminger/prototypes/sky2-0.15-0.16.diff).
It adds a debugging interface /proc/net/sky2/{pci-id} that will show the
pending status
and transmit ring. It would be useful to see what that contains after a hang.
This version also
has some other changes, so the hang might already be fixed.
diff -urNp -X dontdiff git-2.6/drivers/net/sky2.c sky2/drivers/net/sky2.c
--- git-2.6/drivers/net/sky2.c 2006-02-07 11:30:37.000000000 -0800
+++ sky2/drivers/net/sky2.c 2006-02-16 13:53:03.000000000 -0800
@@ -28,6 +28,7 @@
#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
+#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
@@ -51,7 +52,7 @@
#include "sky2.h"
#define DRV_NAME "sky2"
-#define DRV_VERSION "0.15"
+#define DRV_VERSION "0.16"
#define PFX DRV_NAME " "
/*
@@ -232,7 +233,17 @@ static int sky2_set_power_state(struct s
if (hw->ports > 1)
reg1 |= PCI_Y2_PHY2_COMA;
}
+
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+ pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0);
+ pci_read_config_dword(hw->pdev, PCI_DEV_REG4, ®1);
+ reg1 &= P_ASPM_CONTROL_MSK;
+ pci_write_config_dword(hw->pdev, PCI_DEV_REG4, reg1);
+ pci_write_config_dword(hw->pdev, PCI_DEV_REG5, 0);
+ }
+
pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
+
break;
case PCI_D3hot:
@@ -463,16 +474,31 @@ static void sky2_phy_init(struct sky2_hw
ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
}
- gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
+ /* apply fixes in PHY AFE */
+ gm_phy_write(hw, port, 22, 255);
+ /* increase differential signal amplitude in 10BASE-T */
+ gm_phy_write(hw, port, 24, 0xaa99);
+ gm_phy_write(hw, port, 23, 0x2011);
+
+ /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
+ gm_phy_write(hw, port, 24, 0xa204);
+ gm_phy_write(hw, port, 23, 0x2002);
- if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
- /* turn on 100 Mbps LED (LED_LINK100) */
- ledover |= PHY_M_LED_MO_100(MO_LED_ON);
- }
+ /* set page register to 0 */
+ gm_phy_write(hw, port, 22, 0);
+ } else {
+ gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
- if (ledover)
- gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
+ if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed ==
SPEED_100) {
+ /* turn on 100 Mbps LED (LED_LINK100) */
+ ledover |= PHY_M_LED_MO_100(MO_LED_ON);
+ }
+
+ if (ledover)
+ gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
+ }
/* Enable phy interrupt on auto-negotiation complete (or link up) */
if (sky2->autoneg == AUTONEG_ENABLE)
gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
@@ -483,9 +509,9 @@ static void sky2_phy_init(struct sky2_hw
/* Force a renegotiation */
static void sky2_phy_reinit(struct sky2_port *sky2)
{
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
sky2_phy_init(sky2->hw, sky2->port);
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
}
static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
@@ -520,10 +546,16 @@ static void sky2_mac_init(struct sky2_hw
switch (sky2->speed) {
case SPEED_1000:
+ reg &= ~GM_GPCR_SPEED_100;
reg |= GM_GPCR_SPEED_1000;
- /* fallthru */
+ break;
case SPEED_100:
+ reg &= ~GM_GPCR_SPEED_1000;
reg |= GM_GPCR_SPEED_100;
+ break;
+ case SPEED_10:
+ reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
+ break;
}
if (sky2->duplex == DUPLEX_FULL)
@@ -544,9 +576,9 @@ static void sky2_mac_init(struct sky2_hw
sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
sky2_phy_init(hw, port);
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
/* MIB clear */
reg = gma_read16(hw, port, GM_PHY_ADDR);
@@ -601,6 +633,9 @@ static void sky2_mac_init(struct sky2_hw
/* Flush Rx MAC FIFO on any flow control or error */
sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
+ /* Truncate frames after mtu + vlan */
+ sky2_write16(hw, SK_REG(port, RX_GMF_TR_THR), sky2->rx_bufsize/8);
+
/* Set threshold to 0xa (64 bytes)
* ASF disabled so no need to do WA dev #4.30
*/
@@ -859,9 +894,9 @@ static int sky2_ioctl(struct net_device
case SIOCGMIIREG: {
u16 val = 0;
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
data->val_out = val;
break;
@@ -871,10 +906,10 @@ static int sky2_ioctl(struct net_device
if (!capable(CAP_NET_ADMIN))
return -EPERM;
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
data->val_in);
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
break;
}
return err;
@@ -947,6 +982,12 @@ static int sky2_rx_start(struct sky2_por
sky2->rx_put = sky2->rx_next = 0;
sky2_qset(hw, rxq);
+
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
+ /* MAC Rx RAM Read is controlled by hardware */
+ sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
+ }
+
sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
rx_set_checksum(sky2);
@@ -1029,9 +1070,10 @@ static int sky2_up(struct net_device *de
RB_RST_SET);
sky2_qset(hw, txqaddr[port]);
- if (hw->chip_id == CHIP_ID_YUKON_EC_U)
- sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
+ /* Set almost empty threshold */
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
+ sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
TX_RING_SIZE - 1);
@@ -1446,6 +1488,29 @@ static void sky2_link_up(struct sky2_por
sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
reg = gma_read16(hw, port, GM_GP_CTRL);
+ if (sky2->autoneg == AUTONEG_DISABLE) {
+ reg |= GM_GPCR_AU_ALL_DIS;
+
+ /* Is write/read necessary? Copied from sky2_mac_init */
+ gma_write16(hw, port, GM_GP_CTRL, reg);
+ gma_read16(hw, port, GM_GP_CTRL);
+
+ switch (sky2->speed) {
+ case SPEED_1000:
+ reg &= ~GM_GPCR_SPEED_100;
+ reg |= GM_GPCR_SPEED_1000;
+ break;
+ case SPEED_100:
+ reg &= ~GM_GPCR_SPEED_1000;
+ reg |= GM_GPCR_SPEED_100;
+ break;
+ case SPEED_10:
+ reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
+ break;
+ }
+ } else
+ reg &= ~GM_GPCR_AU_ALL_DIS;
+
if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
reg |= GM_GPCR_DUP_FULL;
@@ -1574,7 +1639,7 @@ static void sky2_phy_task(void *arg)
struct sky2_hw *hw = sky2->hw;
u16 istatus, phystat;
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
@@ -1602,7 +1667,7 @@ static void sky2_phy_task(void *arg)
sky2_link_down(sky2);
}
out:
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
local_irq_disable();
hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
@@ -1651,7 +1716,7 @@ static void sky2_tx_timeout(struct net_d
/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan
*/
static inline unsigned sky2_buf_size(int mtu)
{
- return roundup(mtu + ETH_HLEN + 4, 8);
+ return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8);
}
static int sky2_change_mtu(struct net_device *dev, int new_mtu)
@@ -1693,6 +1758,8 @@ static int sky2_change_mtu(struct net_de
gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
+ sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize/8);
+
sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
err = sky2_rx_start(sky2);
@@ -1832,7 +1899,7 @@ static int sky2_poll(struct net_device *
u16 hwidx;
u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
- sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
+ BUG_ON(sky2_read32(hw, B0_IMSK) & Y2_IS_STAT_BMU);
hwidx = sky2_read16(hw, STAT_PUT_IDX);
BUG_ON(hwidx >= STATUS_RING_SIZE);
@@ -1918,14 +1985,22 @@ exit_loop:
if (likely(work_done < to_do)) {
/* need to restart TX timer */
- if (is_ec_a1(hw)) {
+ if (is_ec_a1(hw)
+ && sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
}
- netif_rx_complete(dev0);
+ /*
+ * Need to avoid race where IRQ happens after rx_complete
+ * and before mask update, that leaves IRQ disabled
+ */
+ local_irq_disable();
+ __netif_rx_complete(dev0);
hw->intr_mask |= Y2_IS_STAT_BMU;
sky2_write32(hw, B0_IMSK, hw->intr_mask);
+ local_irq_enable();
+
return 0;
} else {
*budget -= work_done;
@@ -2050,7 +2125,7 @@ static void sky2_mac_intr(struct sky2_hw
}
}
-static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
+static inline void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
{
struct net_device *dev = hw->dev[port];
struct sky2_port *sky2 = netdev_priv(dev);
@@ -2075,13 +2150,16 @@ static irqreturn_t sky2_intr(int irq, vo
/* Do NAPI for Rx and Tx status */
if (status & Y2_IS_STAT_BMU) {
- hw->intr_mask &= ~Y2_IS_STAT_BMU;
- sky2_write32(hw, B0_IMSK, hw->intr_mask);
+ sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
+
+ if (__netif_rx_schedule_prep(dev0)) {
+ hw->intr_mask &= ~Y2_IS_STAT_BMU;
+ sky2_write32(hw, B0_IMSK, hw->intr_mask);
- if (likely(__netif_rx_schedule_prep(dev0))) {
prefetch(&hw->st_le[hw->st_idx]);
__netif_rx_schedule(dev0);
- }
+ } else
+ printk(KERN_DEBUG PFX "napi race?\n");
}
if (status & Y2_IS_IRQ_PHY1)
@@ -2098,8 +2176,6 @@ static irqreturn_t sky2_intr(int irq, vo
sky2_write32(hw, B0_Y2_SP_ICR, 2);
- sky2_read32(hw, B0_IMSK);
-
return IRQ_HANDLED;
}
@@ -2268,6 +2344,7 @@ static int sky2_reset(struct sky2_hw *hw
/* set Status-FIFO ISR watermark */
sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev.
#4.18 */
+ /* WA for dev. #4.3 and #4.18 */
sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
} else {
sky2_write16(hw, STAT_TX_IDX_TH, 10);
@@ -2673,7 +2750,7 @@ static int sky2_phys_id(struct net_devic
ms = data * 1000;
/* save initial values */
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
if (hw->chip_id == CHIP_ID_YUKON_XL) {
u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
@@ -2689,9 +2766,9 @@ static int sky2_phys_id(struct net_devic
sky2_led(hw, port, onoff);
onoff = !onoff;
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
interrupted = msleep_interruptible(250);
- down(&sky2->phy_sema);
+ mutex_lock(&sky2->phy_mutex);
ms -= 250;
}
@@ -2706,7 +2783,7 @@ static int sky2_phys_id(struct net_devic
gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
}
- up(&sky2->phy_sema);
+ mutex_unlock(&sky2->phy_mutex);
return 0;
}
@@ -3019,7 +3096,7 @@ static __devinit struct net_device *sky2
sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
- init_MUTEX(&sky2->phy_sema);
+ mutex_init(&sky2->phy_mutex);
sky2->tx_pending = TX_DEF_PENDING;
sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
@@ -3118,12 +3195,107 @@ static int __devinit sky2_test_msi(struc
return err;
}
+
+static struct proc_dir_entry *sky2_proc;
+
+static int sky2_seq_show(struct seq_file *seq, void *v)
+{
+ const struct sky2_hw *hw = seq->private;
+ unsigned i, idx, hwidx;
+
+ seq_printf(seq, "Intr mask=%#x\n", hw->intr_mask);
+
+ seq_printf(seq, "Status ring:\n");
+ hwidx = sky2_read16(hw, STAT_PUT_IDX);
+ for (idx = hw->st_idx; idx != hwidx; idx = (idx + 1) %
STATUS_RING_SIZE) {
+ const struct sky2_status_le *le = hw->st_le + idx;
+
+ seq_printf(seq, "[%d] %#x %#x %d\n", idx,
+ le->opcode, le32_to_cpu(le->status),
+ le16_to_cpu(le->length));
+ }
+
+ for (i = 0; i < 2; i++) {
+ struct net_device *dev = hw->dev[i];
+ const struct sky2_port *sky2 = netdev_priv(dev);
+
+ if (!netif_running(dev))
+ continue;
+
+ seq_printf(seq, "%s: transmit ring\n", dev->name);
+ idx = sky2->tx_cons;
+ while (idx != sky2->tx_prod) {
+ const struct tx_ring_info *re = sky2->tx_ring + idx;
+ const struct sky2_tx_le *le = sky2->tx_le + idx;
+
+ seq_printf(seq, "[%d]", idx);
+ do {
+ u8 op = le->opcode & ~HW_OWNER;
+
+ seq_putc(seq, ' ');
+
+ if (op & 0x10) {
+ seq_puts(seq, "tcp:");
+ if (op & 1)
+ seq_puts(seq, "write:");
+ if (op & 2)
+ seq_puts(seq, "start:");
+ if (op & 4)
+ seq_puts(seq, "init:");
+ if (op & 8)
+ seq_puts(seq, "lck:");
+ } else {
+ if (op & 2) {
+ seq_puts(seq, "vlan:");
+ op &= ~2;
+ }
+ switch(op) {
+ case OP_ADDR64:
+ seq_puts(seq, "addr64:");
+ break;
+ case OP_LRGLEN:
+ seq_puts(seq, "mss:");
+ break;
+ case OP_LARGESEND:
+ seq_puts(seq, "tso:");
+ break;
+ }
+ }
+
+ seq_printf(seq, "%#x:%d",
+ le32_to_cpu(le->tx.addr),
+ le16_to_cpu(le->length));
+
+ idx = (idx + 1) % TX_RING_SIZE;
+ } while (idx != re->idx && idx != sky2->tx_prod);
+ seq_putc(seq, '\n');
+ }
+ }
+
+ return 0;
+}
+
+static int sky2_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, sky2_seq_show, PDE(inode)->data);
+}
+
+struct file_operations sky2_proc_fops = {
+ .owner = THIS_MODULE,
+ .open = sky2_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
+
static int __devinit sky2_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct net_device *dev, *dev1 = NULL;
struct sky2_hw *hw;
int err, pm_cap, using_dac = 0;
+ struct proc_dir_entry *pe;
err = pci_enable_device(pdev);
if (err) {
@@ -3265,6 +3437,12 @@ static int __devinit sky2_probe(struct p
pci_set_drvdata(pdev, hw);
+ pe = create_proc_entry(pci_name(pdev), S_IRUGO, sky2_proc);
+ if (pe) {
+ pe->proc_fops = &sky2_proc_fops;
+ pe->data = hw;
+ }
+
return 0;
err_out_unregister:
@@ -3299,6 +3477,8 @@ static void __devexit sky2_remove(struct
if (!hw)
return;
+ remove_proc_entry(pci_name(pdev), sky2_proc);
+
dev0 = hw->dev[0];
dev1 = hw->dev[1];
if (dev1)
@@ -3394,12 +3574,15 @@ static struct pci_driver sky2_driver = {
static int __init sky2_init_module(void)
{
+ sky2_proc = proc_mkdir("sky2", proc_net);
+
return pci_register_driver(&sky2_driver);
}
static void __exit sky2_cleanup_module(void)
{
pci_unregister_driver(&sky2_driver);
+ proc_net_remove("sky2");
}
module_init(sky2_init_module);
diff -urNp -X dontdiff git-2.6/drivers/net/sky2.h sky2/drivers/net/sky2.h
--- git-2.6/drivers/net/sky2.h 2006-02-07 11:30:37.000000000 -0800
+++ sky2/drivers/net/sky2.h 2006-02-16 13:19:45.000000000 -0800
@@ -5,14 +5,22 @@
#define _SKY2_H
/* PCI config registers */
-#define PCI_DEV_REG1 0x40
-#define PCI_DEV_REG2 0x44
-#define PCI_DEV_STATUS 0x7c
-#define PCI_OS_PCI_X (1<<26)
-
-#define PEX_LNK_STAT 0xf2
-#define PEX_UNC_ERR_STAT 0x104
-#define PEX_DEV_CTRL 0xe8
+enum {
+ PCI_DEV_REG1 = 0x40,
+ PCI_DEV_REG2 = 0x44,
+ PCI_DEV_STATUS = 0x7c,
+ PCI_DEV_REG3 = 0x80,
+ PCI_DEV_REG4 = 0x84,
+ PCI_DEV_REG5 = 0x88,
+};
+
+enum {
+ PEX_DEV_CAP = 0xe4,
+ PEX_DEV_CTRL = 0xe8,
+ PEX_DEV_STA = 0xea,
+ PEX_LNK_STAT = 0xf2,
+ PEX_UNC_ERR_STAT= 0x104,
+};
/* Yukon-2 */
enum pci_dev_reg_1 {
@@ -37,6 +45,25 @@ enum pci_dev_reg_2 {
PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
};
+/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
+enum pci_dev_reg_4 {
+ /* (Link Training & Status State
Machine) */
+ P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value
Mask */
+ /* (Active State Power Management) */
+ P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
+ P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
+ P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
+ P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
+
+ P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
+ P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
+ P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
+ P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
+ P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
+ P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
+ | P_ASPM_CLKRUN_REQUEST |
P_ASPM_INT_FIFO_EMPTY,
+};
+
#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
@@ -507,6 +534,16 @@ enum {
};
#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
+/* Q_F 32 bit Flag Register */
+enum {
+ F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
+ F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
+ F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
+ F_WM_REACHED = 1<<25, /* Watermark reached */
+ F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
+ F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
+ F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
+};
/* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
enum {
@@ -909,10 +946,12 @@ enum {
PHY_BCOM_ID1_C0 = 0x6044,
PHY_BCOM_ID1_C5 = 0x6047,
- PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
+ PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
- PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
- PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
+ PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
+ PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
+ PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
+ PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
};
/* Advertisement register bits */
@@ -1831,7 +1870,7 @@ struct sky2_port {
struct net_device_stats net_stats;
struct work_struct phy_task;
- struct semaphore phy_sema;
+ struct mutex phy_mutex;
};
struct sky2_hw {
-
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