On Fri, Dec 02, 2005 at 11:04:14AM -0700, Grant Grundler wrote: > At the time you did this, I read the Intel docs on P3 and P4 cache > behaviors. IIRC, the P4 HW prefetches very aggressively. ie the SW > prefetching just becomes noise or burns extra CPU cycles. My guess
I don't think they can follow pointers well. AFAIK all the x86 HW prefetchers just try to detect movements in arrays. One exception is speculative execution where it might follow a pointer sooner, but the look ahead window for that is relatively small In theory software can do better than that. > was the x86 HW designers had exactly the opposite perspective than > the RISC designers had: x86 SW won't change - ie can't add SW controlled > prefetching to improvement perf - therefore HW has to do it. e.g. power4/5/ppc970 do aggressive such prefetching too. -Andi - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
