Author: zoltan
Date: 2008-02-05 14:26:45 -0500 (Tue, 05 Feb 2008)
New Revision: 94930
Modified:
branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.c
branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h
branches/vargaz/mini-linear-il/mono/mono/mini/mini.c
Log:
2008-02-05 Zoltan Varga <[EMAIL PROTECTED]>
* mini.c (mono_normalize_opcodes): New pass to get rid of CEE_ opcodes.
* mini-amd64.c mini-amd64.c: Get rid of CEE_ opcodes.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-05
19:26:18 UTC (rev 94929)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/ChangeLog 2008-02-05
19:26:45 UTC (rev 94930)
@@ -1,5 +1,9 @@
2008-02-05 Zoltan Varga <[EMAIL PROTECTED]>
+ * mini.c (mono_normalize_opcodes): New pass to get rid of CEE_ opcodes.
+
+ * mini-amd64.c mini-amd64.c: Get rid of CEE_ opcodes.
+
* cpu-amd64.md: Fix x86_mul_membase.
* inssel.brg: Pass OP_CALL to backends instead of CEE_CALL.
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.c 2008-02-05
19:26:18 UTC (rev 94929)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.c 2008-02-05
19:26:45 UTC (rev 94930)
@@ -1973,11 +1973,9 @@
*/
ins->opcode = OP_X86_LEA_MEMBASE;
ins->inst_basereg = ins->sreg1;
- /* Fall through */
}
- else
- break;
- case CEE_XOR:
+ break;
+ case OP_LXOR:
if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 ==
ins->dreg)) {
MonoInst *ins2;
@@ -2156,8 +2154,6 @@
}
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
case OP_FMOVE:
/*
@@ -2220,7 +2216,6 @@
}
else
break;
- case CEE_XOR:
case OP_LXOR:
if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 ==
ins->dreg)) {
MonoInst *ins2;
@@ -2383,7 +2378,7 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? CEE_CONV_I1 : CEE_CONV_U1;
+ ins->opcode = (ins->opcode ==
OP_LOADI1_MEMBASE) ? OP_LCONV_TO_I1 : OP_LCONV_TO_U1;
ins->sreg1 = last_ins->sreg1;
}
break;
@@ -2399,12 +2394,10 @@
if (last_ins && (last_ins->opcode ==
OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg ==
last_ins->inst_destbasereg &&
ins->inst_offset ==
last_ins->inst_offset) {
- ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? CEE_CONV_I2 : CEE_CONV_U2;
+ ins->opcode = (ins->opcode ==
OP_LOADI2_MEMBASE) ? OP_LCONV_TO_I2 : OP_LCONV_TO_U2;
ins->sreg1 = last_ins->sreg1;
}
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
case OP_FMOVE:
/*
@@ -2690,7 +2683,6 @@
/* Move return value to the target register */
/* FIXME: do this in the local reg allocator */
switch (ins->opcode) {
- case CEE_CALL:
case OP_CALL:
case OP_CALL_REG:
case OP_CALL_MEMBASE:
@@ -3045,38 +3037,30 @@
case OP_AMD64_LOADI8_MEMINDEX:
amd64_mov_reg_memindex_size (code, ins->dreg,
ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
break;
- case CEE_CONV_I1:
case OP_LCONV_TO_I1:
case OP_ICONV_TO_I1:
case OP_SEXT_I1:
amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE,
FALSE);
break;
- case CEE_CONV_I2:
case OP_LCONV_TO_I2:
case OP_ICONV_TO_I2:
case OP_SEXT_I2:
amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE,
TRUE);
break;
- case CEE_CONV_U1:
case OP_LCONV_TO_U1:
case OP_ICONV_TO_U1:
amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE,
FALSE);
break;
- case CEE_CONV_U2:
case OP_LCONV_TO_U2:
case OP_ICONV_TO_U2:
amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE,
TRUE);
break;
- case CEE_CONV_U8:
- case CEE_CONV_U:
- /* Clean out the upper word */
- amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
- break;
- case CEE_CONV_I8:
- case CEE_CONV_I:
case OP_SEXT_I4:
amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
- break;
+ break;
+ case OP_ZEXT_I4:
+ amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
+ break;
case OP_COMPARE:
case OP_LCOMPARE:
amd64_alu_reg_reg (code, X86_CMP, ins->sreg1,
ins->sreg2);
@@ -3255,7 +3239,6 @@
case OP_NOT_NULL:
break;
case OP_ADDCC:
- case CEE_ADD:
case OP_LADD:
amd64_alu_reg_reg (code, X86_ADD, ins->sreg1,
ins->sreg2);
break;
@@ -3272,7 +3255,6 @@
amd64_alu_reg_imm (code, X86_ADC, ins->dreg,
ins->inst_imm);
break;
case OP_SUBCC:
- case CEE_SUB:
case OP_LSUB:
amd64_alu_reg_reg (code, X86_SUB, ins->sreg1,
ins->sreg2);
break;
@@ -3289,7 +3271,6 @@
amd64_alu_reg_imm (code, X86_SBB, ins->dreg,
ins->inst_imm);
break;
- case CEE_MUL:
case OP_LMUL:
amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
break;
@@ -3356,9 +3337,7 @@
}
break;
}
- case CEE_DIV:
case OP_LDIV:
- case CEE_REM:
case OP_LREM:
/* Regalloc magic makes the div/rem cases the same */
if (ins->sreg2 == AMD64_RDX) {
@@ -3370,9 +3349,7 @@
amd64_div_reg (code, ins->sreg2, TRUE);
}
break;
- case CEE_DIV_UN:
case OP_LDIV_UN:
- case CEE_REM_UN:
case OP_LREM_UN:
if (ins->sreg2 == AMD64_RDX) {
amd64_mov_membase_reg (code, AMD64_RSP, -8,
AMD64_RDX, 8);
@@ -3410,7 +3387,6 @@
EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE,
"OverflowException");
break;
- case CEE_AND:
case OP_LAND:
amd64_alu_reg_reg (code, X86_AND, ins->sreg1,
ins->sreg2);
break;
@@ -3419,7 +3395,6 @@
g_assert (amd64_is_imm32 (ins->inst_imm));
amd64_alu_reg_imm (code, X86_AND, ins->sreg1,
ins->inst_imm);
break;
- case CEE_OR:
case OP_LOR:
amd64_alu_reg_reg (code, X86_OR, ins->sreg1,
ins->sreg2);
break;
@@ -3428,7 +3403,6 @@
g_assert (amd64_is_imm32 (ins->inst_imm));
amd64_alu_reg_imm (code, X86_OR, ins->sreg1,
ins->inst_imm);
break;
- case CEE_XOR:
case OP_LXOR:
amd64_alu_reg_reg (code, X86_XOR, ins->sreg1,
ins->sreg2);
break;
@@ -3438,12 +3412,10 @@
amd64_alu_reg_imm (code, X86_XOR, ins->sreg1,
ins->inst_imm);
break;
- case CEE_SHL:
case OP_LSHL:
g_assert (ins->sreg2 == AMD64_RCX);
amd64_shift_reg (code, X86_SHL, ins->dreg);
break;
- case CEE_SHR:
case OP_LSHR:
g_assert (ins->sreg2 == AMD64_RCX);
amd64_shift_reg (code, X86_SAR, ins->dreg);
@@ -3464,10 +3436,6 @@
g_assert (amd64_is_imm32 (ins->inst_imm));
amd64_shift_reg_imm (code, X86_SHR, ins->dreg,
ins->inst_imm);
break;
- case CEE_SHR_UN:
- g_assert (ins->sreg2 == AMD64_RCX);
- amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
- break;
case OP_LSHR_UN:
g_assert (ins->sreg2 == AMD64_RCX);
amd64_shift_reg (code, X86_SHR, ins->dreg);
@@ -3653,18 +3621,13 @@
amd64_cmov_reg (code, cc_table [mono_opcode_to_cond
(ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg,
ins->sreg2);
break;
- case CEE_NOT:
case OP_LNOT:
amd64_not_reg (code, ins->sreg1);
break;
- case CEE_NEG:
case OP_LNEG:
amd64_neg_reg (code, ins->sreg1);
break;
- case OP_ZEXT_I4:
- amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
- break;
case OP_ICONST:
case OP_I8CONST:
if ((((guint64)ins->inst_c0) >> 32) == 0)
@@ -3680,8 +3643,6 @@
mono_add_patch_info (cfg, offset,
(MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
break;
- case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof
(gpointer));
break;
@@ -3774,7 +3735,6 @@
case OP_VCALL:
case OP_VCALL2:
case OP_VOIDCALL:
- case CEE_CALL:
call = (MonoCallInst*)ins;
/*
* The AMD64 ABI forces callers to know about varargs.
@@ -4051,18 +4011,6 @@
EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table
[ins->opcode - OP_COND_EXC_IEQ],
(ins->opcode <
OP_COND_EXC_INE_UN), ins->inst_p1);
break;
- case CEE_BEQ:
- case CEE_BNE_UN:
- case CEE_BLT:
- case CEE_BLT_UN:
- case CEE_BGT:
- case CEE_BGT_UN:
- case CEE_BGE:
- case CEE_BGE_UN:
- case CEE_BLE:
- case CEE_BLE_UN:
- EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond
(ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
- break;
/* floating point opcodes */
case OP_R8CONST: {
@@ -4145,10 +4093,8 @@
else
amd64_fld_membase (code, ins->inst_basereg,
ins->inst_offset, FALSE);
break;
- case CEE_CONV_R4: /* FIXME: change precision */
case OP_ICONV_TO_R4:
case OP_ICONV_TO_R8:
- case CEE_CONV_R8:
if (use_sse2)
amd64_sse_cvtsi2sd_reg_reg_size (code,
ins->dreg, ins->sreg1, 4);
else {
@@ -4157,10 +4103,6 @@
amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
}
break;
- case CEE_CONV_R_UN:
- /* Emulated */
- g_assert_not_reached ();
- break;
case OP_LCONV_TO_R4: /* FIXME: change precision */
case OP_LCONV_TO_R8:
if (use_sse2)
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h 2008-02-05
19:26:18 UTC (rev 94929)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini-amd64.h 2008-02-05
19:26:45 UTC (rev 94930)
@@ -279,6 +279,7 @@
#define MONO_ARCH_COMMON_VTABLE_TRAMPOLINE 1
#define MONO_ARCH_HAVE_CMOV_OPS 1
#define MONO_ARCH_HAVE_NOTIFY_PENDING_EXC 1
+#define MONO_ARCH_ENABLE_NORMALIZE_OPCODES 1
#define MONO_ARCH_AOT_SUPPORTED 1
Modified: branches/vargaz/mini-linear-il/mono/mono/mini/mini.c
===================================================================
--- branches/vargaz/mini-linear-il/mono/mono/mini/mini.c 2008-02-05
19:26:18 UTC (rev 94929)
+++ branches/vargaz/mini-linear-il/mono/mono/mini/mini.c 2008-02-05
19:26:45 UTC (rev 94930)
@@ -11663,6 +11663,84 @@
mono_mempool_destroy (cfg->state_pool);
}
+/*
+ * mono_normalize_opcodes:
+ *
+ * Replace CEE_ opcodes with the corresponding OP_I or OP_L opcodes.
+ */
+
+static gint16 *remap_table;
+
+#if SIZEOF_VOID_P == 8
+#define REMAP_OPCODE(opcode) OP_L ## opcode
+#else
+#define REMAP_OPCODE(opcode) OP_I ## opcode
+#endif
+
+static void
+mono_normalize_opcodes (MonoCompile *cfg, MonoBasicBlock *bb)
+{
+ MonoInst *ins;
+
+ if (!remap_table) {
+ remap_table = g_new0 (gint16, OP_LAST);
+
+#if SIZEOF_VOID_P == 8
+ remap_table [CEE_CONV_I1] = OP_LCONV_TO_I1;
+ remap_table [CEE_CONV_I2] = OP_LCONV_TO_I2;
+ remap_table [CEE_CONV_U1] = OP_LCONV_TO_U1;
+ remap_table [CEE_CONV_U2] = OP_LCONV_TO_U2;
+ remap_table [CEE_CONV_U8] = OP_ZEXT_I4;
+ remap_table [CEE_CONV_U] = OP_ZEXT_I4;
+ remap_table [CEE_CONV_I8] = OP_SEXT_I4;
+ remap_table [CEE_CONV_I] = OP_SEXT_I4;
+ remap_table [CEE_CONV_R4] = OP_ICONV_TO_R4;
+ remap_table [CEE_CONV_R8] = OP_ICONV_TO_R8;
+ remap_table [CEE_CONV_I4] = OP_MOVE;
+ remap_table [CEE_CONV_U4] = OP_MOVE;
+ remap_table [CEE_CONV_OVF_U4] = OP_LCONV_TO_OVF_U4;
+ remap_table [CEE_CONV_OVF_I4_UN] = OP_LCONV_TO_OVF_I4_UN;
+#else
+ g_assert_not_reached ();
+#endif
+
+ remap_table [CEE_ADD] = REMAP_OPCODE (ADD);
+ remap_table [CEE_SUB] = REMAP_OPCODE (SUB);
+ remap_table [CEE_MUL] = REMAP_OPCODE (MUL);
+ remap_table [CEE_DIV] = REMAP_OPCODE (DIV);
+ remap_table [CEE_REM] = REMAP_OPCODE (REM);
+ remap_table [CEE_DIV_UN] = REMAP_OPCODE (DIV_UN);
+ remap_table [CEE_REM_UN] = REMAP_OPCODE (REM_UN);
+ remap_table [CEE_AND] = REMAP_OPCODE (AND);
+ remap_table [CEE_OR] = REMAP_OPCODE (OR);
+ remap_table [CEE_XOR] = REMAP_OPCODE (XOR);
+ remap_table [CEE_SHL] = REMAP_OPCODE (SHL);
+ remap_table [CEE_SHR] = REMAP_OPCODE (SHR);
+ remap_table [CEE_SHR_UN] = REMAP_OPCODE (SHR_UN);
+ remap_table [CEE_NOT] = REMAP_OPCODE (NOT);
+ remap_table [CEE_NEG] = REMAP_OPCODE (NEG);
+ remap_table [CEE_CALL] = OP_CALL;
+ remap_table [CEE_BEQ] = REMAP_OPCODE (BEQ);
+ remap_table [CEE_BNE_UN] = REMAP_OPCODE (BNE_UN);
+ remap_table [CEE_BLT] = REMAP_OPCODE (BLT);
+ remap_table [CEE_BLT_UN] = REMAP_OPCODE (BLT_UN);
+ remap_table [CEE_BGT] = REMAP_OPCODE (BGT);
+ remap_table [CEE_BGT_UN] = REMAP_OPCODE (BGT_UN);
+ remap_table [CEE_BGE] = REMAP_OPCODE (BGE);
+ remap_table [CEE_BGE_UN] = REMAP_OPCODE (BGE_UN);
+ remap_table [CEE_BLE] = REMAP_OPCODE (BLE);
+ remap_table [CEE_BLE_UN] = REMAP_OPCODE (BLE_UN);
+ }
+
+#ifdef MONO_ARCH_ENABLE_NORMALIZE_OPCODES
+ MONO_BB_FOR_EACH_INS (bb, ins) {
+ int remapped = remap_table [ins->opcode];
+ if (remapped)
+ ins->opcode = remapped;
+ }
+#endif
+}
+
void
mono_codegen (MonoCompile *cfg)
{
@@ -11676,7 +11754,9 @@
/* we reuse dfn here */
/* bb->dfn = bb_count++; */
//if ((bb == cfg->bb_entry) || !(bb->region == -1 && !bb->dfn))
- mono_arch_local_regalloc (cfg, bb);
+ if (!cfg->new_ir)
+ mono_normalize_opcodes (cfg, bb);
+ mono_arch_local_regalloc (cfg, bb);
}
if (cfg->prof_options & MONO_PROFILE_COVERAGE)
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