The following module was proposed for inclusion in the Module List:
modid: Verilog::CodeGen
DSLIP: anphp
description: Object-oriented Verilog code generator
userid: WVDB (Wim Vanderbauwhede)
chapterid: 9 (Language_Interfaces)
communities:
similar:
rationale:
Verilog::CodeGen is a set of modules and scripts to generate
Verilog code in a flexible way. I think it belongs in the Verilog::
namespace because it's and interface to the Verilog language.
Originally I called it DeviceLibs, but I think CodeGen better
reflects the purpose.
It is different from all other Verilog:: modules because it
generates Verilog code, while the other modules work on existing
Verilog code.
The module offers a number of methods to create objects that
generate the Verilog code based on the object's attributes. This
makes it very easy to create completely parametrizable designs. I
think the module is useful for designers doing non-standard Verilog
designs, like asynchronous logic, or analog designs in VerilogA.
A GUI to control the complete process of creating objects, adding
them to the device library, and testing is provided, but the modules
do not require the GUI.
enteredby: WVDB (Wim Vanderbauwhede)
enteredon: Tue Nov 5 11:02:23 2002 GMT
The resulting entry would be:
Verilog::
::CodeGen anphp Object-oriented Verilog code generator WVDB
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