The following module was proposed for inclusion in the Module List:
modid: Verilog::Netlist DSLIP: RdpOp description: Build and access netlist interconnects userid: WSNYDER (Wilson Snyder) chapterid: 9 (Language_Interfaces) communities: similar: rationale: This is a higher level abstraction of the Verilog modules, allowing extraction of netlist information at a higher level then other previous methods. It's also the baseclass for the listed SystemC::Netlist. enteredby: WSNYDER (Wilson Snyder) enteredon: Mon Apr 8 14:04:15 2002 GMT The resulting entry would be: Verilog:: ::Netlist RdpOp Build and access netlist interconnects WSNYDER Thanks for registering, The Pause Team PS: The following links are only valid for module list maintainers: Registration form with editing capabilities: https://pause.perl.org/pause/authenquery?ACTION=add_mod&USERID=62100000_662116b15a21699f&SUBMIT_pause99_add_mod_preview=1 Immediate (one click) registration: https://pause.perl.org/pause/authenquery?ACTION=add_mod&USERID=62100000_662116b15a21699f&SUBMIT_pause99_add_mod_insertit=1