Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
---
docs/GL3.txt | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +-
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 12 ++++++++----
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 549c4db..7387ee2 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -153,7 +153,7 @@ GL 4.3, GLSL 4.30:
GL_ARB_ES3_compatibility DONE (all drivers that
support GLSL 3.30)
GL_ARB_clear_buffer_object DONE (all drivers)
GL_ARB_compute_shader in progress (jljusten)
- GL_ARB_copy_image DONE (i965, radeonsi)
+ GL_ARB_copy_image DONE (i965, nvc0,
radeonsi)
GL_KHR_debug DONE (all drivers)
GL_ARB_explicit_uniform_location DONE (all drivers that
support GLSL)
GL_ARB_fragment_layer_viewport DONE (nv50, nvc0, r600,
radeonsi, llvmpipe)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 93c360e..b08017f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -180,6 +180,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_DEPTH_BOUNDS_TEST:
case PIPE_CAP_TGSI_TXQS:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+ case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
case PIPE_CAP_SHAREABLE_SHADERS:
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
@@ -203,7 +204,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
return 0;
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index dbdf292..3fafa63 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -225,10 +225,14 @@ nvc0_resource_copy_region(struct pipe_context *pipe,
nv04_resource(dst)->status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
if (m2mf) {
+ struct nv50_miptree *src_mt = nv50_miptree(src);
+ struct nv50_miptree *dst_mt = nv50_miptree(dst);
struct nv50_m2mf_rect drect, srect;
unsigned i;
- unsigned nx = util_format_get_nblocksx(src->format, src_box->width);
- unsigned ny = util_format_get_nblocksy(src->format, src_box->height);
+ unsigned nx = util_format_get_nblocksx(src->format, src_box->width)
+ << src_mt->ms_x;
+ unsigned ny = util_format_get_nblocksy(src->format, src_box->height)
+ << src_mt->ms_y;
nv50_m2mf_rect_setup(&drect, dst, dst_level, dstx, dsty, dstz);
nv50_m2mf_rect_setup(&srect, src, src_level,
@@ -237,12 +241,12 @@ nvc0_resource_copy_region(struct pipe_context *pipe,
for (i = 0; i < src_box->depth; ++i) {
nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny);
- if (nv50_miptree(dst)->layout_3d)
+ if (dst_mt->layout_3d)
drect.z++;
else
drect.base += nv50_miptree(dst)->layer_stride;
- if (nv50_miptree(src)->layout_3d)
+ if (src_mt->layout_3d)
srect.z++;
else
srect.base += nv50_miptree(src)->layer_stride;
--
2.4.10
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