On 13/10/15 03:10, Matt Turner wrote:
> On Mon, Oct 12, 2015 at 4:25 PM, Matt Turner <matts...@gmail.com> wrote:
>> On Sat, Oct 10, 2015 at 4:24 AM, Alejandro Piñeiro <apinhe...@igalia.com>
>> wrote:
>>> vec4 port of fs_cmod_propagation.
>>>
>>> Shader-db results:
>>> total instructions in shared programs: 6241226 -> 6224469 (-0.27%)
>>> instructions in affected programs: 498213 -> 481456 (-3.36%)
>>> helped: 3082
>>> HURT: 0
>>> ---
>>>
>>> The final outcome is really similar to fs_brw_cmod_propagation. In
>>> fact the only difference is that on fs we have this:
>>> if (scan_inst->overwrites_reg(inst->src[0])) {
>>> if (scan_inst->is_partial_write() ||
>>> scan_inst->dst.reg_offset != inst->src[0].reg_offset)
>>> break;
>>>
>>> And on vec4 (this commit) we have this:
>>> if (inst->src[0].in_range(scan_inst->dst,
>>> scan_inst->regs_written)) {
>>>
>>> if ((scan_inst->predicate && scan_inst->opcode !=
>>> BRW_OPCODE_SEL) ||
>>> scan_inst->dst.reg_offset != inst->src[0].reg_offset ||
>>> (scan_inst->dst.writemask != WRITEMASK_X &&
>>> scan_inst->dst.writemask != WRITEMASK_XYZW))
>>> break;
>>>
>>> if (scan_inst->dst.writemask == WRITEMASK_XYZW &&
>>> inst->src[0].swizzle != BRW_SWIZZLE_XYZW) {
>>> break;
>>> }
>>>
>>> So at some point I thought about refactoring it and having one common,
>>> like with opt_predicated_break, but that one was possible with just
>>> backend_instructions, while here we would need to deal with
>>> vec4_instructions and fs_inst, that could be somewhat messy, so
>>> I'm leaving this as it is.
>>>
>>> src/mesa/drivers/dri/i965/Makefile.sources | 1 +
>>> src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 +
>>> src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
>>> .../drivers/dri/i965/brw_vec4_cmod_propagation.cpp | 163
>>> +++++++++++++++++++++
>>> 4 files changed, 166 insertions(+)
>>> create mode 100644 src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
>>>
>>> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
>>> b/src/mesa/drivers/dri/i965/Makefile.sources
>>> index 81ef628..c1836d6 100644
>>> --- a/src/mesa/drivers/dri/i965/Makefile.sources
>>> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
>>> @@ -56,6 +56,7 @@ i965_compiler_FILES = \
>>> brw_util.c \
>>> brw_util.h \
>>> brw_vec4_builder.h \
>>> + brw_vec4_cmod_propagation.cpp \
>>> brw_vec4_copy_propagation.cpp \
>>> brw_vec4.cpp \
>>> brw_vec4_cse.cpp \
>>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>>> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>>> index e966b96..55e381b 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
>>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
>>> @@ -1867,6 +1867,7 @@ vec4_visitor::run()
>>> OPT(dead_code_eliminate);
>>> OPT(dead_control_flow_eliminate, this);
>>> OPT(opt_copy_propagation);
>>> + OPT(opt_cmod_propagation);
>>> OPT(opt_cse);
>>> OPT(opt_algebraic);
>>> OPT(opt_register_coalesce);
>>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
>>> b/src/mesa/drivers/dri/i965/brw_vec4.h
>>> index 5e3500c..3c1711d 100644
>>> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
>>> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
>>> @@ -149,6 +149,7 @@ public:
>>> int var_range_start(unsigned v, unsigned n) const;
>>> int var_range_end(unsigned v, unsigned n) const;
>>> bool virtual_grf_interferes(int a, int b);
>>> + bool opt_cmod_propagation();
>>> bool opt_copy_propagation(bool do_constant_prop = true);
>>> bool opt_cse_local(bblock_t *block);
>>> bool opt_cse();
>>> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
>>> b/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
>>> new file mode 100644
>>> index 0000000..7e39d2b
>>> --- /dev/null
>>> +++ b/src/mesa/drivers/dri/i965/brw_vec4_cmod_propagation.cpp
>>> @@ -0,0 +1,163 @@
>>> +/*
>>> + * Copyright © 2015 Intel Corporation
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a
>>> + * copy of this software and associated documentation files (the
>>> "Software"),
>>> + * to deal in the Software without restriction, including without
>>> limitation
>>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>>> + * and/or sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice (including the
>>> next
>>> + * paragraph) shall be included in all copies or substantial portions of
>>> the
>>> + * Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>>> OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>>> OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>>> DEALINGS
>>> + * IN THE SOFTWARE.
>>> + *
>>> + * Authors:
>>> + * Alejandro Piñeiro Iglesias <apinhe...@igalia.com>
>>> + *
>>> + * Based on brw_fs_cmod_propagation.cpp
>>> + */
>>> +
>>> +/** @file brw_vec4_cmod_propagation.cpp
>>> + *
>>> + * Really similar to brw_fs_cmod_propagation but adapted to vec4 needs.
>>> Check
>>> + * brw_fs_cmod_propagation for further details on the rationale behind this
>>> + * optimization.
>>> + */
>>> +
>>> +#include "brw_vec4.h"
>>> +#include "brw_cfg.h"
>>> +
>>> +namespace brw {
>>> +
>>> +static bool
>>> +opt_cmod_propagation_local(bblock_t *block)
>>> +{
>>> + bool progress = false;
>>> + int ip = block->end_ip + 1;
>>> +
>>> + foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
>>> + ip--;
>>> +
>>> + if ((inst->opcode != BRW_OPCODE_AND &&
>>> + inst->opcode != BRW_OPCODE_CMP &&
>>> + inst->opcode != BRW_OPCODE_MOV) ||
>>> + inst->predicate != BRW_PREDICATE_NONE ||
>>> + !inst->dst.is_null() ||
>>> + inst->src[0].file != GRF ||
>>> + inst->src[0].abs)
>>> + continue;
>>> +
>>> + if (inst->opcode == BRW_OPCODE_AND &&
>>> + !(inst->src[1].is_one() &&
>>> + inst->conditional_mod == BRW_CONDITIONAL_NZ &&
>>> + !inst->src[0].negate))
>>> + continue;
>>> +
>>> + if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero())
>>> + continue;
>>> +
>>> + if (inst->opcode == BRW_OPCODE_MOV &&
>>> + inst->conditional_mod != BRW_CONDITIONAL_NZ)
>>> + continue;
>>> +
>>> + bool read_flag = false;
>>> + foreach_inst_in_block_reverse_starting_from(vec4_instruction,
>>> scan_inst, inst,
>>> + block) {
>>> + if (inst->src[0].in_range(scan_inst->dst,
>>> + scan_inst->regs_written)) {
>>> +
>> Extra new line.
Ok.
>>
>>> + if ((scan_inst->predicate && scan_inst->opcode !=
>>> BRW_OPCODE_SEL) ||
>>> + scan_inst->dst.reg_offset != inst->src[0].reg_offset ||
>>> + (scan_inst->dst.writemask != WRITEMASK_X &&
>>> scan_inst->dst.writemask != WRITEMASK_XYZW))
>> Line wrap this.
Ok.
>>
>>> + break;
>>> +
>>> + if (scan_inst->dst.writemask == WRITEMASK_XYZW &&
>>> + inst->src[0].swizzle != BRW_SWIZZLE_XYZW) {
>>> + break;
>>> + }
>> I'd just combine both of these blocks:
>>
>> if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) ||
>> scan_inst->dst.reg_offset != inst->src[0].reg_offset ||
>> (scan_inst->dst.writemask != WRITEMASK_X &&
>> scan_inst->dst.writemask != WRITEMASK_XYZW) ||
>> (scan_inst->dst.writemask == WRITEMASK_XYZW &&
>> inst->src[0].swizzle != BRW_SWIZZLE_XYZW))
>> break;
Ok.
>>
>> But I believe it's correct (if maybe conservative).
>>
>> Reviewed-by: Matt Turner <matts...@gmail.com>
> Looks like this is causing an intermittent failure on HSW in our
> Jenkins system (but I'm not able to reproduce locally) and a
> consistent failure on G45. I'll investigate that.
Ok, will hold on, and meanwhile I will try to reproduce the problem on
HSW. Unfortunately I don't have any G45 available, so I will not be able
to help on that. Thanks for taking a look there.
Best regards
--
Alejandro Piñeiro (apinhe...@igalia.com)
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