On Sat, Oct 10, 2015 at 1:17 PM, Matt Turner <matts...@gmail.com> wrote: > Curro added this in commit 3ee2daf23d (before the vec4/NIR backend was > added) but it was missed in the new NIR backend. Add it there as well. > > instructions in affected programs: 1857 -> 1810 (-2.53%) > helped: 15 > --- > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > index 41bd80d..fdf767d 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp > @@ -1237,14 +1237,8 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) > break; > > case nir_op_b2i: > - emit(AND(dst, op[0], src_reg(1))); > - break; > - > case nir_op_b2f: > - op[0].type = BRW_REGISTER_TYPE_D; > - dst.type = BRW_REGISTER_TYPE_D; > - emit(AND(dst, op[0], src_reg(0x3f800000u))); > - dst.type = BRW_REGISTER_TYPE_F; > + emit(MOV(dst, negate(op[0])));
For my own edification, could you explain how this works? Let's say you have a sequence like... bool b = ...; /* b contains 0 or ~0 "internally" */ int x = floatBitsToInt((float)b) + 1; Thanks, -ilia > break; > > case nir_op_f2b: > -- > 2.4.9 > > _______________________________________________ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/mesa-dev _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
