When preparing the barrier payload, the instructions should operate in
simd8 mode since we only use 1 payload register.
fs_inst::regs_read is also updated to indicate that it only reads one
register for SHADER_OPCODE_BARRIER.
These issues were flagged by:
commit cadd7dd384b33a779d46bd664f456bed4a21a5b7
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Jul 2 15:41:02 2015 -0700
i965/fs: Add a very basic validation pass
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Jason Ekstrand <jason.ekstr...@intel.com>
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 6 ++++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 63bee0a..b4d0567 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -797,6 +797,7 @@ fs_inst::regs_read(int arg) const
break;
case CS_OPCODE_CS_TERMINATE:
+ case SHADER_OPCODE_BARRIER:
return 1;
default:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 8b61c86..b85b52b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1045,12 +1045,14 @@ fs_visitor::emit_barrier()
fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ const fs_builder pbld = bld.exec_all().group(8, 0);
+
/* Clear the message payload */
- bld.exec_all().MOV(payload, fs_reg(0u));
+ pbld.MOV(payload, fs_reg(0u));
/* Copy bits 27:24 of r0.2 (barrier id) to the message payload reg.2 */
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
- bld.exec_all().AND(component(payload, 2), r0_2, fs_reg(0x0f000000u));
+ pbld.AND(component(payload, 2), r0_2, fs_reg(0x0f000000u));
/* Emit a gateway "barrier" message using the payload we set up, followed
* by a wait instruction.
--
2.5.0
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