Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
---
src/mesa/drivers/dri/i965/brw_defines.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index a8594af..7b07c50 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2396,6 +2396,26 @@ enum brw_wm_barycentric_interp_mode {
#define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */
#define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */
+/* Resource streamer gather constants */
+#define _3DSTATE_GATHER_POOL_ALLOC 0x791A /* GEN7.5+ */
+#define _3DSTATE_GATHER_CONSTANT_VS 0x7834
+#define _3DSTATE_GATHER_CONSTANT_GS 0x7835
+#define _3DSTATE_GATHER_CONSTANT_HS 0x7836
+#define _3DSTATE_GATHER_CONSTANT_DS 0x7837
+#define _3DSTATE_GATHER_CONSTANT_PS 0x7838
+/* Only required in HSW */
+#define HSW_GATHER_CONSTANTS_RESERVED (3 << 4)
+
+#define BRW_GATHER_CONSTANTS_ENABLE (1 << 11) /* GEN7.5+ */
+#define BRW_GATHER_BUFFER_VALID_SHIFT 16
+#define BRW_GATHER_BUFFER_VALID_MASK INTEL_MASK(31, 16)
+#define BRW_GATHER_BINDING_TABLE_BLOCK_SHIFT 12
+#define BRW_GATHER_BINDING_TABLE_BLOCK_MASK INTEL_MASK(15, 12)
+#define BRW_GATHER_CONST_BUFFER_OFFSET_SHIFT 8
+#define BRW_GATHER_CONST_BUFFER_OFFSET_MASK INTEL_MASK(15, 8)
+#define BRW_GATHER_CHANNEL_MASK_SHIFT 4
+#define BRW_GATHER_CHANNEL_MASK_MASK INTEL_MASK(7, 4)
+
#define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */
/* DW1 */
# define SO_FUNCTION_ENABLE (1 << 31)
--
1.9.1
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