On Wed, Sep 9, 2015 at 7:18 PM, Ian Romanick <i...@freedesktop.org> wrote:
> From: Ian Romanick <ian.d.roman...@intel.com>
>
> The target parameter of compute_msaa_layout appears to be unused since
> 83b83fb when support for CMS textures was added for Gen7.
>
> The brw parameter of intel_get_non_msrt_mcs_alignment appears to be
> unused since e92fbdc when the GEN check (along with the "can we fast
> clear" decision) was moved to a different function.
>
> intel_mipmap_tree.c: In function 'compute_msaa_layout':
> intel_mipmap_tree.c:62:73: warning: unused parameter 'target'
> [-Wunused-parameter]
> compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum
> target,
> ^
> intel_mipmap_tree.c: In function 'intel_get_non_msrt_mcs_alignment':
> intel_mipmap_tree.c:143:54: warning: unused parameter 'brw'
> [-Wunused-parameter]
> intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> ^
>
> Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
> Cc: Ben Widawsky <benjamin.widaw...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++++----
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 ++++-----
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +--
> 3 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> index f5ecbb5..eb20173 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> @@ -204,7 +204,7 @@ brw_draw_rectlist(struct gl_context *ctx, struct rect
> *rect, int num_instances)
> }
>
> static void
> -get_fast_clear_rect(struct brw_context *brw, struct gl_framebuffer *fb,
> +get_fast_clear_rect(struct gl_framebuffer *fb,
> struct intel_renderbuffer *irb, struct rect *rect)
> {
> unsigned int x_align, y_align;
> @@ -226,7 +226,7 @@ get_fast_clear_rect(struct brw_context *brw, struct
> gl_framebuffer *fb,
> * alignment size returned by intel_get_non_msrt_mcs_alignment(),
> but
> * with X alignment multiplied by 16 and Y alignment multiplied by
> 32.
> */
> - intel_get_non_msrt_mcs_alignment(brw, irb->mt, &x_align, &y_align);
> + intel_get_non_msrt_mcs_alignment(irb->mt, &x_align, &y_align);
> x_align *= 16;
> y_align *= 32;
>
> @@ -516,7 +516,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct
> gl_framebuffer *fb,
> irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
> irb->need_downsample = true;
> fast_clear_buffers |= 1 << index;
> - get_fast_clear_rect(brw, fb, irb, &fast_clear_rect);
> + get_fast_clear_rect(fb, irb, &fast_clear_rect);
> break;
>
> case REP_CLEAR:
> @@ -653,7 +653,7 @@ get_resolve_rect(struct brw_context *brw,
> * by 8 and 16 and 8 and 8 for SKL.
> */
>
> - intel_get_non_msrt_mcs_alignment(brw, mt, &x_align, &y_align);
> + intel_get_non_msrt_mcs_alignment(mt, &x_align, &y_align);
> if (brw->gen >= 9) {
> x_scaledown = x_align * 8;
> y_scaledown = y_align * 8;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 19f66b7..485752f 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -59,7 +59,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
> * created, based on the chip generation and the surface type.
> */
> static enum intel_msaa_layout
> -compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum
> target,
> +compute_msaa_layout(struct brw_context *brw, mesa_format format,
> bool disable_aux_buffers)
> {
> /* Prior to Gen7, all MSAA surfaces used IMS layout. */
> @@ -140,8 +140,7 @@ compute_msaa_layout(struct brw_context *brw,
> mesa_format format, GLenum target,
> * by half the block width, and Y coordinates by half the block height.
> */
> void
> -intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> - struct intel_mipmap_tree *mt,
> +intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
> unsigned *width_px, unsigned *height)
> {
> switch (mt->tiling) {
> @@ -322,7 +321,7 @@ intel_miptree_create_layout(struct brw_context *brw,
> if (num_samples > 1) {
> /* Adjust width/height/depth for MSAA */
> mt->msaa_layout = compute_msaa_layout(brw, format,
> - mt->target,
> mt->disable_aux_buffers);
> + mt->disable_aux_buffers);
> if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
> /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
> * "If the surface is multisampled and it is a depth or stencil
> @@ -1427,7 +1426,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
> *brw,
> const mesa_format format = MESA_FORMAT_R_UINT32;
> unsigned block_width_px;
> unsigned block_height;
> - intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px,
> &block_height);
> + intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
> unsigned width_divisor = block_width_px * 4;
> unsigned height_divisor = block_height * 8;
> unsigned mcs_width =
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index c28162a..81e5f52 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -517,8 +517,7 @@ struct intel_mipmap_tree
> };
>
> void
> -intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
> - struct intel_mipmap_tree *mt,
> +intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
> unsigned *width_px, unsigned *height);
> bool
> intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned
> tiling);
> --
> 2.1.0
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
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