https://bugs.freedesktop.org/show_bug.cgi?id=91254
--- Comment #15 from Jordan Justen <jljus...@gmail.com> ---
(In reply to Chris Wilson from comment #14)
> diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
> b/src/mesa/drivers/dri/i965/brw_misc_state.c
> index e9d9467..2751152 100644
> --- a/src/mesa/drivers/dri/i965/brw_misc_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
> @@ -878,7 +878,8 @@ brw_upload_invariant_state(struct brw_context *brw)
> {
> const bool is_965 = brw->gen == 4 && !brw->is_g4x;
>
> - brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
> + brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
> + brw->last_pipeline = BRW_RENDER_PIPELINE;
>
> if (brw->gen < 6) {
> /* Disable depth offset clamping. */
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index 9de42ce..7577cfc 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -423,9 +423,6 @@ void brw_init_state( struct brw_context *brw )
> {
> struct gl_context *ctx = &brw->ctx;
>
> - /* Force the first brw_select_pipeline to emit pipeline select */
> - brw->last_pipeline = BRW_NUM_PIPELINES;
> -
> STATIC_ASSERT(ARRAY_SIZE(gen4_atoms) <= ARRAY_SIZE(brw->render_atoms));
> STATIC_ASSERT(ARRAY_SIZE(gen6_atoms) <= ARRAY_SIZE(brw->render_atoms));
> STATIC_ASSERT(ARRAY_SIZE(gen7_render_atoms) <=
brw_init_state calls brw_upload_initial_gpu_state
which calls brw_upload_invariant_state, which calls
brw_select_pipeline(brw, BRW_RENDER_PIPELINE), so
this should be the same, right?
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