It takes care of using the correct tile width if we later use other
tiling patterns for aux miptree.
V2: Remove the comment about using Yf for aux miptree.
Cc: Ben Widawsky <b...@bwidawsk.net>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 6c4d3e1..aadea1a 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -262,8 +262,13 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
}
if (aux_mt) {
+ uint32_t tile_w, tile_h;
+ assert(aux_mt->tiling == I915_TILING_Y);
+ intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
+ aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
- SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ SET_FIELD((aux_mt->pitch / tile_w) - 1,
+ GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;
@@ -487,8 +492,13 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
}
if (aux_mt) {
+ uint32_t tile_w, tile_h;
+ assert(aux_mt->tiling == I915_TILING_Y);
+ intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
+ aux_mt->cpp, &tile_w, &tile_h);
surf[6] = SET_FIELD(mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
- SET_FIELD((aux_mt->pitch / 128) - 1, GEN8_SURFACE_AUX_PITCH) |
+ SET_FIELD((aux_mt->pitch / tile_w) - 1,
+ GEN8_SURFACE_AUX_PITCH) |
aux_mode;
} else {
surf[6] = 0;
--
2.4.3
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