We have accurate dirty tracking for normal render buffers and textures
within a batch, and so for when we only need to do a normal invalidation
of the texture cache before the next primitive we can remove the manual
flushes. We have to keep the flushes required for changing certain bits
of internal GPU state and also keep the explicit flush for operating on
random buffers (as we only track flushes required for certain sources
like the texture, if the user blits into a buffer bound elsewhere (like
the vertex buffer) we have to explicitly flush).
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/intel_blit.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index d95e5aa5..4d1defc 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -667,8 +667,6 @@ intelEmitCopyBlit(struct brw_context *brw,
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
- brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
-
return brw_batch_end(&brw->batch) == 0;
}
@@ -747,8 +745,6 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
brw_batch_data(&brw->batch, src_bits, dwords * 4);
- brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
-
return brw_batch_end(&brw->batch) == 0;
}
@@ -863,7 +859,5 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
- brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
-
brw_batch_end(&brw->batch);
}
--
2.5.0
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
