Francisco Jerez <curroje...@riseup.net> writes: > Ping. Some 10-20 other ARB_shader_image_load_store patches are blocking > on this patch I've been carrying around since I originally sent it for > review in Dec 2013. > Hint for reviewers: A quick comparison with "i965/fs: Import image memory offset calculation code." [1] should be enough to convince oneself that it's sensible.
[1] http://lists.freedesktop.org/archives/mesa-dev/2015-July/089793.html > Francisco Jerez <curroje...@riseup.net> writes: > >> This will be used to pass image meta-data to the shader when we cannot >> use typed surface reads and writes. All entries except surface_idx >> and size are otherwise unused and will get eliminated by the uniform >> packing pass. size will be used for bounds checking with some image >> formats and will be useful for ARB_shader_image_size too. surface_idx >> is always used. >> --- >> src/mesa/drivers/dri/i965/brw_context.h | 50 +++++++++++++++ >> src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 78 >> ++++++++++++++++++++++++ >> 2 files changed, 128 insertions(+) >> >> diff --git a/src/mesa/drivers/dri/i965/brw_context.h >> b/src/mesa/drivers/dri/i965/brw_context.h >> index 8cc54ad..e12528e 100644 >> --- a/src/mesa/drivers/dri/i965/brw_context.h >> +++ b/src/mesa/drivers/dri/i965/brw_context.h >> @@ -370,6 +370,52 @@ struct brw_stage_prog_data { >> const gl_constant_value **pull_param; >> }; >> >> +/* >> + * Image meta-data structure as laid out in the shader parameter >> + * buffer. Entries have to be 16B-aligned for the vec4 back-end to be >> + * able to use them. That's okay because the padding and any unused >> + * entries [most of them except when we're doing untyped surface >> + * access] will be removed by the uniform packing pass. >> + */ >> +#define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0 >> +#define BRW_IMAGE_PARAM_OFFSET_OFFSET 4 >> +#define BRW_IMAGE_PARAM_SIZE_OFFSET 8 >> +#define BRW_IMAGE_PARAM_STRIDE_OFFSET 12 >> +#define BRW_IMAGE_PARAM_TILING_OFFSET 16 >> +#define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20 >> +#define BRW_IMAGE_PARAM_SIZE 24 >> + >> +struct brw_image_param { >> + /** Surface binding table index. */ >> + uint32_t surface_idx; >> + >> + /** Surface X, Y and Z dimensions. */ >> + uint32_t size[3]; >> + >> + /** Offset applied to the X and Y surface coordinates. */ >> + uint32_t offset[2]; >> + >> + /** X-stride in bytes, Y-stride in bytes, horizontal slice stride in >> + * pixels, vertical slice stride in pixels. >> + */ >> + uint32_t stride[4]; >> + >> + /** Log2 of the tiling modulus in the X, Y and Z dimension. */ >> + uint32_t tiling[3]; >> + >> + /** >> + * Right shift to apply for bit 6 address swizzling. Two different >> + * swizzles can be specified and will be applied one after the other. >> The >> + * resulting address will be: >> + * >> + * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^ >> + * (addr >> swizzling[1]))) >> + * >> + * Use \c 0xff if any of the swizzles is not required. >> + */ >> + uint32_t swizzling[2]; >> +}; >> + >> /* Data about a particular attempt to compile a program. Note that >> * there can be many of these, each in a different GL state >> * corresponding to a different brw_wm_prog_key struct, with different >> @@ -944,6 +990,10 @@ struct brw_stage_state >> /** SAMPLER_STATE count and table offset */ >> uint32_t sampler_count; >> uint32_t sampler_offset; >> + >> + /** Metadata for images passed to the shader as uniforms. */ >> + struct brw_image_param image_params[BRW_MAX_IMAGES]; >> + uint32_t nr_image_params; >> }; >> >> >> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c >> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c >> index 13755aa..50636aa 100644 >> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c >> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c >> @@ -981,6 +981,79 @@ get_image_format(struct brw_context *brw, mesa_format >> format, GLenum access) >> } >> >> static void >> +update_default_image_param(struct brw_context *brw, >> + struct gl_image_unit *u, >> + unsigned surface_idx, >> + struct brw_image_param *param) >> +{ >> + memset(param, 0, sizeof(*param)); >> + param->surface_idx = surface_idx; >> + param->swizzling[0] = 0xff; >> + param->swizzling[1] = 0xff; >> +} >> + >> +static void >> +update_buffer_image_param(struct brw_context *brw, >> + struct gl_image_unit *u, >> + unsigned surface_idx, >> + struct brw_image_param *param) >> +{ >> + struct gl_buffer_object *obj = u->TexObj->BufferObject; >> + >> + update_default_image_param(brw, u, surface_idx, param); >> + >> + param->size[0] = obj->Size / _mesa_get_format_bytes(u->_ActualFormat); >> + param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat); >> +} >> + >> +static void >> +update_texture_image_param(struct brw_context *brw, >> + struct gl_image_unit *u, >> + unsigned surface_idx, >> + struct brw_image_param *param) >> +{ >> + struct intel_mipmap_tree *mt = intel_texture_object(u->TexObj)->mt; >> + >> + update_default_image_param(brw, u, surface_idx, param); >> + >> + param->size[0] = minify(mt->logical_width0, u->Level); >> + param->size[1] = minify(mt->logical_height0, u->Level); >> + param->size[2] = (!u->Layered ? 1 : >> + u->TexObj->Target == GL_TEXTURE_CUBE_MAP ? 6 : >> + u->TexObj->Target == GL_TEXTURE_3D ? >> + minify(mt->logical_depth0, u->Level) : >> + mt->logical_depth0); >> + >> + intel_miptree_get_image_offset(mt, u->Level, u->Layer, >> + ¶m->offset[0], >> + ¶m->offset[1]); >> + >> + param->stride[0] = mt->cpp; >> + param->stride[1] = mt->pitch / mt->cpp; >> + param->stride[2] = >> + brw_miptree_get_horizontal_slice_pitch(brw, mt, u->Level); >> + param->stride[3] = >> + brw_miptree_get_vertical_slice_pitch(brw, mt, u->Level); >> + >> + if (mt->tiling == I915_TILING_X) { >> + param->tiling[0] = ffs(512 / mt->cpp) - 1; >> + param->tiling[1] = 3; >> + param->swizzling[0] = 3; >> + param->swizzling[1] = 4; >> + } else if (mt->tiling == I915_TILING_Y) { >> + param->tiling[0] = ffs(16 / mt->cpp) - 1; >> + param->tiling[1] = 5; >> + param->swizzling[0] = 3; >> + param->swizzling[1] = 0xff; >> + } >> + >> + if (u->TexObj->Target == GL_TEXTURE_3D) >> + param->tiling[2] = u->Level; >> + else >> + param->tiling[2] = 0; >> +} >> + >> +static void >> update_image_surface(struct brw_context *brw, >> struct gl_image_unit *u, >> GLenum access, >> @@ -1003,6 +1076,8 @@ update_image_surface(struct brw_context *brw, >> format, intel_obj->Base.Size / texel_size, texel_size, >> access != GL_READ_ONLY); >> >> + update_buffer_image_param(brw, u, surface_idx, param); >> + >> } else { >> struct intel_texture_object *intel_obj = intel_texture_object(obj); >> struct intel_mipmap_tree *mt = intel_obj->mt; >> @@ -1030,10 +1105,13 @@ update_image_surface(struct brw_context *brw, >> format, SWIZZLE_XYZW, >> surf_offset, access != GL_READ_ONLY, false); >> } >> + >> + update_texture_image_param(brw, u, surface_idx, param); >> } >> >> } else { >> brw->vtbl.emit_null_surface_state(brw, 1, 1, 1, surf_offset); >> + update_default_image_param(brw, u, surface_idx, param); >> } >> } >> >> -- >> 2.1.3 >> >> _______________________________________________ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
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